From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X084x-0007kI-Lq for qemu-devel@nongnu.org; Thu, 26 Jun 2014 07:43:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X084t-0000N1-QE for qemu-devel@nongnu.org; Thu, 26 Jun 2014 07:42:59 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48729) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X084t-0000MD-Jc for qemu-devel@nongnu.org; Thu, 26 Jun 2014 07:42:55 -0400 From: Peter Maydell Date: Thu, 26 Jun 2014 12:42:45 +0100 Message-Id: <1403782966-20457-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1403782966-20457-1-git-send-email-peter.maydell@linaro.org> References: <1403782966-20457-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 3/4] hw/arm/pxa2xx_gpio: Fix handling of GPSR/GPCR reads List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org The PXA2xx GPIO GPSR and GPCR registers are write-only, with reads being undefined behaviour. Instead of having GPCR return 31337 and GPSR return the value last written, make both log the guest error and return 0. Signed-off-by: Peter Maydell --- hw/arm/pxa2xx_gpio.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c index 7f75f05..cd506df 100644 --- a/hw/arm/pxa2xx_gpio.c +++ b/hw/arm/pxa2xx_gpio.c @@ -36,7 +36,6 @@ struct PXA2xxGPIOInfo { uint32_t rising[PXA2XX_GPIO_BANKS]; uint32_t falling[PXA2XX_GPIO_BANKS]; uint32_t status[PXA2XX_GPIO_BANKS]; - uint32_t gpsr[PXA2XX_GPIO_BANKS]; uint32_t gafr[PXA2XX_GPIO_BANKS * 2]; uint32_t prev_level[PXA2XX_GPIO_BANKS]; @@ -162,14 +161,14 @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset, return s->dir[bank]; case GPSR: /* GPIO Pin-Output Set registers */ - printf("%s: Read from a write-only register " REG_FMT "\n", - __FUNCTION__, offset); - return s->gpsr[bank]; /* Return last written value. */ + qemu_log_mask(LOG_GUEST_ERROR, + "pxa2xx GPIO: read from write only register GPSR\n"); + return 0; case GPCR: /* GPIO Pin-Output Clear registers */ - printf("%s: Read from a write-only register " REG_FMT "\n", - __FUNCTION__, offset); - return 31337; /* Specified as unpredictable in the docs. */ + qemu_log_mask(LOG_GUEST_ERROR, + "pxa2xx GPIO: read from write only register GPCR\n"); + return 0; case GRER: /* GPIO Rising-Edge Detect Enable registers */ return s->rising[bank]; @@ -217,7 +216,6 @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset, case GPSR: /* GPIO Pin-Output Set registers */ s->olevel[bank] |= value; pxa2xx_gpio_handler_update(s); - s->gpsr[bank] = value; break; case GPCR: /* GPIO Pin-Output Clear registers */ -- 1.9.2