From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42932) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1azl-0004Ex-UN for qemu-devel@nongnu.org; Mon, 30 Jun 2014 08:47:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1azi-0005sn-Mj for qemu-devel@nongnu.org; Mon, 30 Jun 2014 08:47:41 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48766) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1azi-0005rQ-FS for qemu-devel@nongnu.org; Mon, 30 Jun 2014 08:47:38 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1X1azb-0008Sl-La for qemu-devel@nongnu.org; Mon, 30 Jun 2014 13:47:31 +0100 From: Peter Maydell Date: Mon, 30 Jun 2014 13:47:25 +0100 Message-Id: <1404132451-32498-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1404132451-32498-1-git-send-email-peter.maydell@linaro.org> References: <1404132451-32498-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 2/8] hw/arm/strongarm: Fix handling of GPSR/GPCR reads List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The StrongARM GPIO GPSR and GPCR registers are write-only, with reads being undefined behaviour. Instead of having GPCR return 31337 and GPSR return the value last written, make both log the guest error and return 0. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- hw/arm/strongarm.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 0da9015..cc2d7f2 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -480,7 +480,6 @@ struct StrongARMGPIOInfo { uint32_t rising; uint32_t falling; uint32_t status; - uint32_t gpsr; uint32_t gafr; uint32_t prev_level; @@ -544,14 +543,14 @@ static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, return s->dir; case GPSR: /* GPIO Pin-Output Set registers */ - DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n", - __func__, offset); - return s->gpsr; /* Return last written value. */ + qemu_log_mask(LOG_GUEST_ERROR, + "strongarm GPIO: read from write only register GPSR\n"); + return 0; case GPCR: /* GPIO Pin-Output Clear registers */ - DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n", - __func__, offset); - return 31337; /* Specified as unpredictable in the docs. */ + qemu_log_mask(LOG_GUEST_ERROR, + "strongarm GPIO: read from write only register GPCR\n"); + return 0; case GRER: /* GPIO Rising-Edge Detect Enable registers */ return s->rising; @@ -590,7 +589,6 @@ static void strongarm_gpio_write(void *opaque, hwaddr offset, case GPSR: /* GPIO Pin-Output Set registers */ s->olevel |= value; strongarm_gpio_handler_update(s); - s->gpsr = value; break; case GPCR: /* GPIO Pin-Output Clear registers */ -- 1.9.1