From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53238) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kis-0005m5-6G for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kim-0003Jk-Vg for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:54 -0400 Received: from mail-ob0-f171.google.com ([209.85.214.171]:58031) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kim-0003JM-Ia for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:48 -0400 Received: by mail-ob0-f171.google.com with SMTP id nu7so9686352obb.30 for ; Mon, 30 Jun 2014 16:10:48 -0700 (PDT) From: greg.bellows@linaro.org Date: Mon, 30 Jun 2014 18:09:12 -0500 Message-Id: <1404169773-20264-13-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v4 12/33] target-arm: use dedicated target_el function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org From: Fabian Aggeler Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/helper.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4233ae3..456b7e7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3444,14 +3444,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_pl(env); unsigned int target_el = 1; + unsigned int target_mode; bool route_to_el2 = false; - /* FIXME: Use actual secure state. */ - bool secure = false; - if (!env->aarch64) { - /* TODO: Add EL2 and 3 exception handling for AArch32. */ - return 1; - } + bool secure = arm_is_secure(env); if (!secure && arm_feature(env, ARM_FEATURE_EL2) @@ -3473,18 +3469,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) } break; case EXCP_FIQ: - case EXCP_IRQ: { - const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO; - const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ; - - if (!secure && (env->cp15.hcr_el2 & hcr_mask)) { - target_el = 2; - } - if (env->cp15.scr_el3 & scr_mask) { - target_el = 3; - } - break; - } + case EXCP_IRQ: + target_el = arm_phys_excp_target_el(cs, &target_mode, excp_idx, + cur_el, secure); + break; case EXCP_VIRQ: case EXCP_VFIQ: target_el = 1; -- 1.8.3.2