From: greg.bellows@linaro.org
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com,
Fabian Aggeler <aggelerf@ethz.ch>,
Greg Bellows <greg.bellows@linaro.org>,
serge.fdrv@gmail.com, edgar.iglesias@gmail.com,
christoffer.dall@linaro.org
Subject: [Qemu-devel] [PATCH v4 01/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions
Date: Mon, 30 Jun 2014 18:09:01 -0500 [thread overview]
Message-ID: <1404169773-20264-2-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org>
From: Fabian Aggeler <aggelerf@ethz.ch>
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
target-arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d77be99..46ee1fe 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -551,6 +551,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fb767;
cpu->reset_fpsid = 0x410120b5;
cpu->mvfr0 = 0x11111111;
@@ -637,6 +638,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fc080;
cpu->reset_fpsid = 0x410330c0;
cpu->mvfr0 = 0x11110222;
@@ -703,6 +705,7 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
/* Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
@@ -769,6 +772,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
cpu->reset_fpsid = 0x410430f0;
--
1.8.3.2
next prev parent reply other threads:[~2014-06-30 23:10 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-30 23:09 [Qemu-devel] [PATCH v4 00/33] target-arm: add Security Extensions for CPUs greg.bellows
2014-06-30 23:09 ` greg.bellows [this message]
2014-09-02 16:34 ` [Qemu-devel] [PATCH v4 01/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions Peter Maydell
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 02/33] target-arm: move Aarch32 SCR into security reglist greg.bellows
2014-07-01 8:15 ` Edgar E. Iglesias
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 03/33] target-arm: increase arrays of registers R13 & R14 greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 04/33] target-arm: add arm_is_secure() function greg.bellows
2014-07-01 8:17 ` Edgar E. Iglesias
2014-07-01 13:51 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 05/33] target-arm: reject switching to monitor mode greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 06/33] target-arm: make arm_current_pl() return PL3 greg.bellows
2014-08-26 14:29 ` Peter Maydell
2014-08-28 13:53 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 07/33] target-arm: add non-secure Translation Block flag greg.bellows
2014-07-01 8:19 ` Edgar E. Iglesias
2014-09-02 16:11 ` Peter Maydell
2014-09-02 16:43 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 08/33] target-arm: A32: Emulate the SMC instruction greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 09/33] target-arm: extend Aarch32 async excp masking greg.bellows
2014-07-01 8:22 ` Edgar E. Iglesias
2014-07-01 13:33 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 10/33] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 11/33] target-arm: add async excp target_el&mode function greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 12/33] target-arm: use dedicated target_el function greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 13/33] target-arm: implement IRQ/FIQ routing to Monitor mode greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 14/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 15/33] target-arm: add NSACR register greg.bellows
2014-07-07 9:40 ` Aggeler Fabian
2014-07-07 14:15 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 16/33] target-arm: add SDER definition greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 17/33] target-arm: add MVBAR support greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 18/33] target-arm: add macros to access banked registers greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 19/33] target-arm: insert Aarch32 cpregs twice into hashtable greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 20/33] target-arm: arrayfying fieldoffset for banking greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 21/33] target-arm: add SCTLR_EL3 and make SCTLR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 22/33] target-arm: make CSSELR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 23/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 24/33] target-arm: add TCR_EL3 and make TTBCR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 25/33] target-arm: make c2_mask and c2_base_mask banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 26/33] target-arm: make DACR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 27/33] target-arm: make IFSR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 28/33] target-arm: make DFSR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 29/33] target-arm: make IFAR/DFAR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 30/33] target-arm: make PAR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 31/33] target-arm: make VBAR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 32/33] target-arm: make c13 cp regs banked (FCSEIDR, ...) greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate CP regs greg.bellows
2014-07-02 9:41 ` [Qemu-devel] [PATCH v4 00/33] target-arm: add Security Extensions for CPUs Aggeler Fabian
2014-09-05 17:55 ` Peter Maydell
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