From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53746) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjE-0006MH-D3 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kj8-0003b4-Mn for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:16 -0400 Received: from mail-oa0-f44.google.com ([209.85.219.44]:49799) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kj8-0003ao-Ig for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:10 -0400 Received: by mail-oa0-f44.google.com with SMTP id i7so9750021oag.31 for ; Mon, 30 Jun 2014 16:11:10 -0700 (PDT) From: greg.bellows@linaro.org Date: Mon, 30 Jun 2014 18:09:22 -0500 Message-Id: <1404169773-20264-23-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v4 22/33] target-arm: make CSSELR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org From: Fabian Aggeler Rename CSSELR (cache size selection register) and add secure instance (Aarch32). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 9 +++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1fcccc8..bc8291a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -177,7 +177,15 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint64_t c0_cssel; /* Cache size selection. */ + union { /* Cache size selection */ + struct { + uint64_t csselr_ns; + uint64_t csselr_s; + }; + struct { + uint64_t csselr_el1; + }; + }; union { /* System control register. */ struct { uint64_t sctlr_ns; diff --git a/target-arm/helper.c b/target-arm/helper.c index 3b663f1..4a3b463 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -700,7 +700,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); - return cpu->ccsidr[env->cp15.c0_cssel]; + return cpu->ccsidr[A32_BANKED_REG_GET(env, csselr)]; } static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -808,10 +808,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, - { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, + { .name = "CSSELR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), - .writefn = csselr_write, .resetvalue = 0 }, + .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), + offsetof(CPUARMState, cp15.csselr_el1) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now * just RAZ for all cores: */ -- 1.8.3.2