From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53993) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjO-0006eY-Vt for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kjJ-0003nj-JM for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:26 -0400 Received: from mail-oa0-f51.google.com ([209.85.219.51]:42526) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjJ-0003n1-7R for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:21 -0400 Received: by mail-oa0-f51.google.com with SMTP id j17so9656670oag.38 for ; Mon, 30 Jun 2014 16:11:21 -0700 (PDT) From: greg.bellows@linaro.org Date: Mon, 30 Jun 2014 18:09:27 -0500 Message-Id: <1404169773-20264-28-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v4 27/33] target-arm: make IFSR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org From: Fabian Aggeler When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 9 +++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 05eebdf..7935915 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -257,7 +257,15 @@ typedef struct CPUARMState { uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ uint32_t scr_el3; /* Secure configuration register. */ - uint32_t ifsr_el2; /* Fault status registers. */ + union { /* Fault status registers. */ + struct { + uint32_t ifsr_ns; + uint32_t ifsr_s; + }; + struct { + uint32_t ifsr32_el2; + }; + }; uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[4]; /* Fault address registers. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 79bf844..fea2d59 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1506,8 +1506,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), .resetfn = arm_cp_reset_ignore, }, { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, - .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, }, + .access = PL1_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifsr_s), + offsetof(CPUARMState, cp15.ifsr_ns) } }, { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, .access = PL1_RW, @@ -3870,11 +3871,11 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.fsr = 2; /* Fall through to prefetch abort. */ case EXCP_PREFETCH_ABORT: - env->cp15.ifsr_el2 = env->exception.fsr; + A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", - env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress); + env->exception.fsr, (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; addr = 0x0c; mask = CPSR_A | CPSR_I; -- 1.8.3.2