From: greg.bellows@linaro.org
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com,
Greg Bellows <greg.bellows@linaro.org>,
serge.fdrv@gmail.com, edgar.iglesias@gmail.com,
christoffer.dall@linaro.org
Subject: [Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate CP regs
Date: Mon, 30 Jun 2014 18:09:33 -0500 [thread overview]
Message-ID: <1404169773-20264-34-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org>
From: Greg Bellows <greg.bellows@linaro.org>
This patch adds code to mark duplicate CP register registrations as NO_MIGRATE
to avoid duplicate migrations.
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
target-arm/helper.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3bc55fe..7c1e2eb 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2339,7 +2339,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
.access = PL3_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
.resetvalue = 0 },
- { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
+ /* SCR will always be registered for v7, but not necessarily for v8, so
+ * this entry is marked to allow migration to be handled by the v7
+ * registration instance.
+ */
+ { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
.writefn = scr_write },
@@ -2958,6 +2962,11 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
* banked registers but later only fieldoffset is used.
*/
r2->fieldoffset = r->bank_fieldoffsets[nsbit];
+ } else if (!nsbit) {
+ /* The register is not banked so we only want to allow migration of
+ * the non-secure instance.
+ */
+ r2->type |= ARM_CP_NO_MIGRATE;
}
if (r->state == ARM_CP_STATE_BOTH) {
--
1.8.3.2
next prev parent reply other threads:[~2014-06-30 23:11 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-30 23:09 [Qemu-devel] [PATCH v4 00/33] target-arm: add Security Extensions for CPUs greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 01/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions greg.bellows
2014-09-02 16:34 ` Peter Maydell
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 02/33] target-arm: move Aarch32 SCR into security reglist greg.bellows
2014-07-01 8:15 ` Edgar E. Iglesias
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 03/33] target-arm: increase arrays of registers R13 & R14 greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 04/33] target-arm: add arm_is_secure() function greg.bellows
2014-07-01 8:17 ` Edgar E. Iglesias
2014-07-01 13:51 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 05/33] target-arm: reject switching to monitor mode greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 06/33] target-arm: make arm_current_pl() return PL3 greg.bellows
2014-08-26 14:29 ` Peter Maydell
2014-08-28 13:53 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 07/33] target-arm: add non-secure Translation Block flag greg.bellows
2014-07-01 8:19 ` Edgar E. Iglesias
2014-09-02 16:11 ` Peter Maydell
2014-09-02 16:43 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 08/33] target-arm: A32: Emulate the SMC instruction greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 09/33] target-arm: extend Aarch32 async excp masking greg.bellows
2014-07-01 8:22 ` Edgar E. Iglesias
2014-07-01 13:33 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 10/33] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 11/33] target-arm: add async excp target_el&mode function greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 12/33] target-arm: use dedicated target_el function greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 13/33] target-arm: implement IRQ/FIQ routing to Monitor mode greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 14/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 15/33] target-arm: add NSACR register greg.bellows
2014-07-07 9:40 ` Aggeler Fabian
2014-07-07 14:15 ` Greg Bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 16/33] target-arm: add SDER definition greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 17/33] target-arm: add MVBAR support greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 18/33] target-arm: add macros to access banked registers greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 19/33] target-arm: insert Aarch32 cpregs twice into hashtable greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 20/33] target-arm: arrayfying fieldoffset for banking greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 21/33] target-arm: add SCTLR_EL3 and make SCTLR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 22/33] target-arm: make CSSELR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 23/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 24/33] target-arm: add TCR_EL3 and make TTBCR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 25/33] target-arm: make c2_mask and c2_base_mask banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 26/33] target-arm: make DACR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 27/33] target-arm: make IFSR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 28/33] target-arm: make DFSR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 29/33] target-arm: make IFAR/DFAR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 30/33] target-arm: make PAR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 31/33] target-arm: make VBAR banked greg.bellows
2014-06-30 23:09 ` [Qemu-devel] [PATCH v4 32/33] target-arm: make c13 cp regs banked (FCSEIDR, ...) greg.bellows
2014-06-30 23:09 ` greg.bellows [this message]
2014-07-02 9:41 ` [Qemu-devel] [PATCH v4 00/33] target-arm: add Security Extensions for CPUs Aggeler Fabian
2014-09-05 17:55 ` Peter Maydell
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