From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjb-0006vL-Q6 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kjV-0003zp-NU for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:39 -0400 Received: from mail-oa0-f52.google.com ([209.85.219.52]:64247) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjV-0003zb-H3 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:33 -0400 Received: by mail-oa0-f52.google.com with SMTP id j17so9714774oag.11 for ; Mon, 30 Jun 2014 16:11:33 -0700 (PDT) From: greg.bellows@linaro.org Date: Mon, 30 Jun 2014 18:09:33 -0500 Message-Id: <1404169773-20264-34-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate CP regs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org From: Greg Bellows This patch adds code to mark duplicate CP register registrations as NO_MIGRATE to avoid duplicate migrations. Signed-off-by: Greg Bellows --- target-arm/helper.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3bc55fe..7c1e2eb 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2339,7 +2339,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue = 0 }, - { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, + /* SCR will always be registered for v7, but not necessarily for v8, so + * this entry is marked to allow migration to be handled by the v7 + * registration instance. + */ + { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .writefn = scr_write }, @@ -2958,6 +2962,11 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, * banked registers but later only fieldoffset is used. */ r2->fieldoffset = r->bank_fieldoffsets[nsbit]; + } else if (!nsbit) { + /* The register is not banked so we only want to allow migration of + * the non-secure instance. + */ + r2->type |= ARM_CP_NO_MIGRATE; } if (r->state == ARM_CP_STATE_BOTH) { -- 1.8.3.2