From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, viro@ZenIV.linux.org.uk
Subject: [Qemu-devel] [PATCH v2 9/9] target-alpha: Fix integer overflow checking insns
Date: Thu, 3 Jul 2014 13:29:07 -0700 [thread overview]
Message-ID: <1404419347-18265-10-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1404419347-18265-1-git-send-email-rth@twiddle.net>
We need to write the result to the destination register before
raising any exception. Thus inline the code for each insn, and
check for any exception after we're done.
Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/helper.h | 7 +-----
target-alpha/int_helper.c | 59 ++--------------------------------------------
target-alpha/translate.c | 60 +++++++++++++++++++++++++++++++++++++++++------
3 files changed, 56 insertions(+), 70 deletions(-)
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 173db01..2cc100b 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -1,12 +1,7 @@
DEF_HELPER_3(excp, noreturn, env, int, int)
DEF_HELPER_FLAGS_1(load_pcc, TCG_CALL_NO_RWG_SE, i64, env)
-DEF_HELPER_FLAGS_3(addqv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(addlv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(subqv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(sublv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(mullv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(mulqv, TCG_CALL_NO_WG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(check_overflow, TCG_CALL_NO_WG, void, env, i64, i64)
DEF_HELPER_FLAGS_1(ctpop, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(ctlz, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target-alpha/int_helper.c b/target-alpha/int_helper.c
index 7a205eb..8e4537f 100644
--- a/target-alpha/int_helper.c
+++ b/target-alpha/int_helper.c
@@ -249,64 +249,9 @@ uint64_t helper_unpkbw(uint64_t op1)
| ((op1 & 0xff000000) << 24));
}
-uint64_t helper_addqv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
+void helper_check_overflow(CPUAlphaState *env, uint64_t op1, uint64_t op2)
{
- uint64_t tmp = op1;
- op1 += op2;
- if (unlikely((tmp ^ op2 ^ (-1ULL)) & (tmp ^ op1) & (1ULL << 63))) {
+ if (unlikely(op1 != op2)) {
arith_excp(env, GETPC(), EXC_M_IOV, 0);
}
- return op1;
-}
-
-uint64_t helper_addlv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
- uint64_t tmp = op1;
- op1 = (uint32_t)(op1 + op2);
- if (unlikely((tmp ^ op2 ^ (-1UL)) & (tmp ^ op1) & (1UL << 31))) {
- arith_excp(env, GETPC(), EXC_M_IOV, 0);
- }
- return op1;
-}
-
-uint64_t helper_subqv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
- uint64_t res;
- res = op1 - op2;
- if (unlikely((op1 ^ op2) & (res ^ op1) & (1ULL << 63))) {
- arith_excp(env, GETPC(), EXC_M_IOV, 0);
- }
- return res;
-}
-
-uint64_t helper_sublv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
- uint32_t res;
- res = op1 - op2;
- if (unlikely((op1 ^ op2) & (res ^ op1) & (1UL << 31))) {
- arith_excp(env, GETPC(), EXC_M_IOV, 0);
- }
- return res;
-}
-
-uint64_t helper_mullv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
- int64_t res = (int64_t)op1 * (int64_t)op2;
-
- if (unlikely((int32_t)res != res)) {
- arith_excp(env, GETPC(), EXC_M_IOV, 0);
- }
- return (int64_t)((int32_t)res);
-}
-
-uint64_t helper_mulqv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
- uint64_t tl, th;
-
- muls64(&tl, &th, op1, op2);
- /* If th != 0 && th != -1, then we had an overflow */
- if (unlikely((th + 1) > 1)) {
- arith_excp(env, GETPC(), EXC_M_IOV, 0);
- }
- return tl;
}
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 183573d..6ea33f3 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1377,7 +1377,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
uint16_t fn11;
uint8_t opc, ra, rb, rc, fpfn, fn7, lit;
bool islit;
- TCGv va, vb, vc, tmp;
+ TCGv va, vb, vc, tmp, tmp2;
TCGv_i32 t32;
ExitStatus ret;
@@ -1589,11 +1589,23 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x40:
/* ADDL/V */
- gen_helper_addlv(vc, cpu_env, va, vb);
+ tmp = tcg_temp_new();
+ tcg_gen_ext32s_i64(tmp, va);
+ tcg_gen_ext32s_i64(vc, vb);
+ tcg_gen_add_i64(tmp, tmp, vc);
+ tcg_gen_ext32s_i64(vc, tmp);
+ gen_helper_check_overflow(cpu_env, vc, tmp);
+ tcg_temp_free(tmp);
break;
case 0x49:
/* SUBL/V */
- gen_helper_sublv(vc, cpu_env, va, vb);
+ tmp = tcg_temp_new();
+ tcg_gen_ext32s_i64(tmp, va);
+ tcg_gen_ext32s_i64(vc, vb);
+ tcg_gen_sub_i64(tmp, tmp, vc);
+ tcg_gen_ext32s_i64(vc, tmp);
+ gen_helper_check_overflow(cpu_env, vc, tmp);
+ tcg_temp_free(tmp);
break;
case 0x4D:
/* CMPLT */
@@ -1601,11 +1613,33 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x60:
/* ADDQ/V */
- gen_helper_addqv(vc, cpu_env, va, vb);
+ tmp = tcg_temp_new();
+ tmp2 = tcg_temp_new();
+ tcg_gen_eqv_i64(tmp, va, vb);
+ tcg_gen_mov_i64(tmp2, va);
+ tcg_gen_add_i64(vc, va, vb);
+ tcg_gen_xor_i64(tmp2, tmp2, vc);
+ tcg_gen_and_i64(tmp, tmp, tmp2);
+ tcg_gen_shri_i64(tmp, tmp, 63);
+ tcg_gen_movi_i64(tmp2, 0);
+ gen_helper_check_overflow(cpu_env, tmp, tmp2);
+ tcg_temp_free(tmp);
+ tcg_temp_free(tmp2);
break;
case 0x69:
/* SUBQ/V */
- gen_helper_subqv(vc, cpu_env, va, vb);
+ tmp = tcg_temp_new();
+ tmp2 = tcg_temp_new();
+ tcg_gen_xor_i64(tmp, va, vb);
+ tcg_gen_mov_i64(tmp2, va);
+ tcg_gen_sub_i64(vc, va, vb);
+ tcg_gen_xor_i64(tmp2, tmp2, vc);
+ tcg_gen_and_i64(tmp, tmp, tmp2);
+ tcg_gen_shri_i64(tmp, tmp, 63);
+ tcg_gen_movi_i64(tmp2, 0);
+ gen_helper_check_overflow(cpu_env, tmp, tmp2);
+ tcg_temp_free(tmp);
+ tcg_temp_free(tmp2);
break;
case 0x6D:
/* CMPLE */
@@ -1900,11 +1934,23 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x40:
/* MULL/V */
- gen_helper_mullv(vc, cpu_env, va, vb);
+ tmp = tcg_temp_new();
+ tcg_gen_ext32s_i64(tmp, va);
+ tcg_gen_ext32s_i64(vc, vb);
+ tcg_gen_mul_i64(tmp, tmp, vc);
+ tcg_gen_ext32s_i64(vc, tmp);
+ gen_helper_check_overflow(cpu_env, vc, tmp);
+ tcg_temp_free(tmp);
break;
case 0x60:
/* MULQ/V */
- gen_helper_mulqv(vc, cpu_env, va, vb);
+ tmp = tcg_temp_new();
+ tmp2 = tcg_temp_new();
+ tcg_gen_muls2_i64(vc, tmp, va, vb);
+ tcg_gen_sari_i64(tmp2, vc, 63);
+ gen_helper_check_overflow(cpu_env, tmp, tmp2);
+ tcg_temp_free(tmp);
+ tcg_temp_free(tmp2);
break;
default:
goto invalid_opc;
--
1.9.3
prev parent reply other threads:[~2014-07-03 20:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-03 20:28 [Qemu-devel] [PATCH v2 0/9] target-alpha exception improvements Richard Henderson
2014-07-03 20:28 ` [Qemu-devel] [PATCH v2 1/9] target-alpha: Forget installed round mode after MT_FPCR Richard Henderson
2014-07-03 20:29 ` [Qemu-devel] [PATCH v2 2/9] target-alpha: Set PC correctly for floating-point exceptions Richard Henderson
2014-07-03 20:29 ` [Qemu-devel] [PATCH v2 3/9] target-alpha: Store IOV exception in fp_status Richard Henderson
2014-07-03 20:29 ` [Qemu-devel] [PATCH v2 4/9] target-alpha: Set fpcr_exc_status even for disabled exceptions Richard Henderson
2014-07-03 20:29 ` [Qemu-devel] [PATCH v2 5/9] target-alpha: Set EXC_M_SWC for exceptions from /S insns Richard Henderson
2014-07-03 20:29 ` [Qemu-devel] [PATCH v2 6/9] target-alpha: Raise IOV from CVTTQ Richard Henderson
2014-07-03 20:29 ` [Qemu-devel] [PATCH v2 7/9] target-alpha: Fix cvttq vs large integers Richard Henderson
2014-07-03 20:29 ` [Qemu-devel] [PATCH v2 8/9] target-alpha: Fix cvttq vs inf Richard Henderson
2014-07-03 20:29 ` Richard Henderson [this message]
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