[Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format.

[Bastian Koppelmann <kbastian@mail.uni-paderborn.de>]

Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for indirect loads.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 7553870..39f29bb 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -116,6 +116,26 @@ static int sign_extend(uint32_t val, uint32_t width)
 /*
  * Functions to generate micro-ops
  */
+
+/* Functions for load/save to/from memory */
+#define OP_MEM_INDIRECT(insn)                                             \
+static inline void gen_indirect_##insn(DisasContext *ctx, TCGv r1, TCGv r2, \
+                                       int16_t con)                       \
+{                                                                         \
+    TCGv temp = tcg_temp_new();                                           \
+    TCGv tempPC = tcg_const_i32(ctx->pc);                                 \
+    tcg_gen_addi_tl(temp, r2, con);                                         \
+    tcg_gen_qemu_##insn(r1, temp, ctx->mem_idx);                            \
+    tcg_temp_free(tempPC);                                                \
+    tcg_temp_free(temp);                                                  \
+}
+OP_MEM_INDIRECT(ld8s)
+OP_MEM_INDIRECT(ld8u)
+OP_MEM_INDIRECT(ld16s)
+OP_MEM_INDIRECT(ld16u)
+OP_MEM_INDIRECT(ld32s)
+OP_MEM_INDIRECT(ld32u)
+
 /* Functions for arithmetic instructions  */
 
 #define OP_COND(insn)\
@@ -489,6 +509,38 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
         tcg_gen_qemu_st32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
         tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
         break;
+/* SRRS-format */
+    case OPC1_16_SRRS_ADDSC_A:
+        r2 = MASK_OP_SRRS_S2(ctx->opcode);
+        r1 = MASK_OP_SRRS_S1D(ctx->opcode);
+        const16 = MASK_OP_SRRS_N(ctx->opcode);
+        temp = tcg_temp_new();
+        tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
+        tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
+
+        tcg_temp_free(temp);
+        break;
+/* SLRO-format */
+    case OPC1_16_SLRO_LD_A:
+        r1 = MASK_OP_SLRO_D(ctx->opcode);
+        const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+        gen_indirect_ld32s(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4);
+        break;
+    case OPC1_16_SLRO_LD_BU:
+        r1 = MASK_OP_SLRO_D(ctx->opcode);
+        const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+        gen_indirect_ld8u(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16);
+        break;
+    case OPC1_16_SLRO_LD_H:
+        r1 = MASK_OP_SLRO_D(ctx->opcode);
+        const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+        gen_indirect_ld16s(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2);
+        break;
+    case OPC1_16_SLRO_LD_W:
+        r1 = MASK_OP_SLRO_D(ctx->opcode);
+        const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+        gen_indirect_ld32s(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4);
+        break;
     }
 }
 
-- 
2.0.1