[Qemu-devel] [PATCH 08/15] target-tricore: Add instructions of SSR opcode format

[Bastian Koppelmann <kbastian@mail.uni-paderborn.de>]

Add instructions of SSR opcode format.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 108619c..7553870 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -432,6 +432,63 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
         r2 = MASK_OP_SRR_S2(ctx->opcode);
         tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
         break;
+/* SSR-format */
+    case OPC1_16_SSR_ST_A:
+        r1 = MASK_OP_SSR_S1(ctx->opcode);
+        r2 = MASK_OP_SSR_S2(ctx->opcode);
+        tcg_gen_qemu_st32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx);
+        break;
+    case OPC1_16_SSR_ST_A_POSTINC:
+        r1 = MASK_OP_SSR_S1(ctx->opcode);
+        r2 = MASK_OP_SSR_S2(ctx->opcode);
+        tcg_gen_qemu_st32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+        break;
+    case OPC1_16_SSR_ST_B:
+        r1 = MASK_OP_SSR_S1(ctx->opcode);
+        r2 = MASK_OP_SSR_S2(ctx->opcode);
+        temp = tcg_temp_new();
+        tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
+        tcg_gen_qemu_st8(temp, cpu_gpr_a[r2], ctx->mem_idx);
+        tcg_temp_free(temp);
+        break;
+    case OPC1_16_SSR_ST_B_POSTINC:
+        r1 = MASK_OP_SSR_S1(ctx->opcode);
+        r2 = MASK_OP_SSR_S2(ctx->opcode);
+        temp = tcg_temp_new();
+        tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
+        tcg_gen_qemu_st8(temp, cpu_gpr_a[r2], ctx->mem_idx);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+        tcg_temp_free(temp);
+        break;
+    case OPC1_16_SSR_ST_H:
+        r1 = MASK_OP_SSR_S1(ctx->opcode);
+        r2 = MASK_OP_SSR_S2(ctx->opcode);
+        temp = tcg_temp_new();
+        tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff);
+        tcg_gen_qemu_st16(temp, cpu_gpr_a[r2], ctx->mem_idx);
+        tcg_temp_free(temp);
+        break;
+    case OPC1_16_SSR_ST_H_POSTINC:
+        r1 = MASK_OP_SSR_S1(ctx->opcode);
+        r2 = MASK_OP_SSR_S2(ctx->opcode);
+        temp = tcg_temp_new();
+        tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff);
+        tcg_gen_qemu_st16(temp, cpu_gpr_a[r2], ctx->mem_idx);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+        tcg_temp_free(temp);
+        break;
+    case OPC1_16_SSR_ST_W:
+        r2 = MASK_OP_SSR_S2(ctx->opcode);
+        r1 = MASK_OP_SSR_S1(ctx->opcode);
+        tcg_gen_qemu_st32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+        break;
+    case OPC1_16_SSR_ST_W_POSTINC:
+        r2 = MASK_OP_SSR_S2(ctx->opcode);
+        r1 = MASK_OP_SSR_S1(ctx->opcode);
+        tcg_gen_qemu_st32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+        break;
     }
 }
 
-- 
2.0.1