From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47541) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4CRC-0004Rk-Bf for qemu-devel@nongnu.org; Mon, 07 Jul 2014 13:10:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X4CR4-0005Xh-6H for qemu-devel@nongnu.org; Mon, 07 Jul 2014 13:10:46 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:10607) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4CR3-0005XJ-QE for qemu-devel@nongnu.org; Mon, 07 Jul 2014 13:10:38 -0400 From: Bastian Koppelmann Date: Mon, 7 Jul 2014 19:13:35 +0100 Message-Id: <1404756822-3253-9-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1404756822-3253-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1404756822-3253-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH 08/15] target-tricore: Add instructions of SSR opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Add instructions of SSR opcode format. Signed-off-by: Bastian Koppelmann --- target-tricore/translate.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 108619c..7553870 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -432,6 +432,63 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx) r2 = MASK_OP_SRR_S2(ctx->opcode); tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; +/* SSR-format */ + case OPC1_16_SSR_ST_A: + r1 = MASK_OP_SSR_S1(ctx->opcode); + r2 = MASK_OP_SSR_S2(ctx->opcode); + tcg_gen_qemu_st32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx); + break; + case OPC1_16_SSR_ST_A_POSTINC: + r1 = MASK_OP_SSR_S1(ctx->opcode); + r2 = MASK_OP_SSR_S2(ctx->opcode); + tcg_gen_qemu_st32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); + break; + case OPC1_16_SSR_ST_B: + r1 = MASK_OP_SSR_S1(ctx->opcode); + r2 = MASK_OP_SSR_S2(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff); + tcg_gen_qemu_st8(temp, cpu_gpr_a[r2], ctx->mem_idx); + tcg_temp_free(temp); + break; + case OPC1_16_SSR_ST_B_POSTINC: + r1 = MASK_OP_SSR_S1(ctx->opcode); + r2 = MASK_OP_SSR_S2(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff); + tcg_gen_qemu_st8(temp, cpu_gpr_a[r2], ctx->mem_idx); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); + tcg_temp_free(temp); + break; + case OPC1_16_SSR_ST_H: + r1 = MASK_OP_SSR_S1(ctx->opcode); + r2 = MASK_OP_SSR_S2(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff); + tcg_gen_qemu_st16(temp, cpu_gpr_a[r2], ctx->mem_idx); + tcg_temp_free(temp); + break; + case OPC1_16_SSR_ST_H_POSTINC: + r1 = MASK_OP_SSR_S1(ctx->opcode); + r2 = MASK_OP_SSR_S2(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff); + tcg_gen_qemu_st16(temp, cpu_gpr_a[r2], ctx->mem_idx); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); + tcg_temp_free(temp); + break; + case OPC1_16_SSR_ST_W: + r2 = MASK_OP_SSR_S2(ctx->opcode); + r1 = MASK_OP_SSR_S1(ctx->opcode); + tcg_gen_qemu_st32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx); + break; + case OPC1_16_SSR_ST_W_POSTINC: + r2 = MASK_OP_SSR_S2(ctx->opcode); + r1 = MASK_OP_SSR_S1(ctx->opcode); + tcg_gen_qemu_st32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); + break; } } -- 2.0.1