From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4QIi-0007am-Rb for qemu-devel@nongnu.org; Tue, 08 Jul 2014 03:59:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X4QIc-0002Fp-4z for qemu-devel@nongnu.org; Tue, 08 Jul 2014 03:58:56 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:57613) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4QIb-0002Ff-Tq for qemu-devel@nongnu.org; Tue, 08 Jul 2014 03:58:50 -0400 From: Leon Alrae Date: Tue, 8 Jul 2014 08:57:37 +0100 Message-ID: <1404806257-28048-10-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1404806257-28048-1-git-send-email-leon.alrae@imgtec.com> References: <1404806257-28048-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 9/9] target-mips: update cpu_save/cpu_load to support new registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net Signed-off-by: Leon Alrae --- target-mips/cpu.h | 2 +- target-mips/machine.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 656f5ca..23bb22c 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -557,7 +557,7 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); -#define CPU_SAVE_VERSION 4 +#define CPU_SAVE_VERSION 5 /* MMU modes definitions. We carefully match the indices with our hflags layout. */ diff --git a/target-mips/machine.c b/target-mips/machine.c index 0496faa..576dc10 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -26,6 +26,8 @@ static void save_tc(QEMUFile *f, TCState *tc) qemu_put_betls(f, &tc->CP0_TCScheFBack); qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); qemu_put_betls(f, &tc->CP0_UserLocal); + qemu_put_be32s(f, &tc->CP0_BadInstr); + qemu_put_be32s(f, &tc->CP0_BadInstrP); } static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) @@ -144,6 +146,9 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_sbe32s(f, &env->CP0_DataHi); qemu_put_betls(f, &env->CP0_ErrorEPC); qemu_put_sbe32s(f, &env->CP0_DESAVE); + for (i = 0; i < MIPS_KSCRATCH_NUM; i++) { + qemu_put_betls(f, &env->CP0_KScratch[i]); + } /* Save inactive TC state */ for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) @@ -177,6 +182,10 @@ static void load_tc(QEMUFile *f, TCState *tc, int version_id) if (version_id >= 4) { qemu_get_betls(f, &tc->CP0_UserLocal); } + if (version_id >= 5) { + qemu_get_be32s(f, &tc->CP0_BadInstr); + qemu_get_be32s(f, &tc->CP0_BadInstrP); + } } static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) @@ -301,6 +310,11 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_sbe32s(f, &env->CP0_DataHi); qemu_get_betls(f, &env->CP0_ErrorEPC); qemu_get_sbe32s(f, &env->CP0_DESAVE); + if (version_id >= 5) { + for (i = 0; i < MIPS_KSCRATCH_NUM; i++) { + qemu_get_betls(f, &env->CP0_KScratch[i]); + } + } /* Load inactive TC state */ for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) { -- 1.7.5.4