[Qemu-devel] [PULL for-2.1 00/18] target-alpha patch queue

[Qemu-devel] [PULL for-2.1 00/18] target-alpha patch queue

[Richard Henderson]

The queue consists of Al Viro's recent work looking at the dark
corner cases of Alpha FPU exception signalling, for which I am
most grateful.

Please pull for 2.1.


r~


The following changes since commit 9d9de254c2b81b68cd48f2324cc753a570a4cdd8:

  MAINTAINERS: seccomp: change email contact for Eduardo Otubo (2014-07-03 12:36:15 +0100)

are available in the git repository at:

  git://github.com/rth7680/qemu.git axp-next

for you to fetch changes up to e465bbb9a96d000b9884a47a037ab92574fb89f7:

  target-alpha: Remove DNOD bit from FPCR (2014-07-09 08:40:09 -0700)

----------------------------------------------------------------
Richard Henderson (18):
      target-alpha: Forget installed round mode after MT_FPCR
      target-alpha: Set PC correctly for floating-point exceptions
      target-alpha: Store IOV exception in fp_status
      target-alpha: Set fpcr_exc_status even for disabled exceptions
      target-alpha: Set EXC_M_SWC for exceptions from /S insns
      target-alpha: Raise IOV from CVTTQ
      target-alpha: Fix cvttq vs large integers
      target-alpha: Fix cvttq vs inf
      target-alpha: Fix integer overflow checking insns
      target-alpha: Implement WH64EN
      target-alpha: Disallow literal operand to 1C.30 to 1C.37
      target-alpha: Ignore the unused fp_status exceptions
      target-alpha: Raise EXC_M_INV properly for fp inputs
      target-alpha: Suppress underflow from CVTTQ if DNZ
      target-alpha: Raise IOV from CVTQL
      target-alpha: Rename fcvtql
      target-alpha: Fix fpcr_flush_to_zero initialization
      target-alpha: Remove DNOD bit from FPCR

 include/fpu/softfloat.h   |  13 ++--
 target-alpha/cpu.h        |   1 -
 target-alpha/fpu_helper.c | 139 +++++++++++++++++++--------------
 target-alpha/helper.c     |  19 +++--
 target-alpha/helper.h     |  12 +--
 target-alpha/int_helper.c |  59 +-------------
 target-alpha/mem_helper.c |   9 ++-
 target-alpha/translate.c  | 191 +++++++++++++++++++++++++++-------------------
 8 files changed, 227 insertions(+), 216 deletions(-)

[Qemu-devel] [PULL 01/18] target-alpha: Forget installed round mode after MT_FPCR

[Richard Henderson]

When we use QUAL_RM_D, we copy fpcr_dyn_round to float_status.
When we install a new FPCR value, we update fpcr_dyn_round.
Reset the status of the cache so that we re-copy for the next
fp insn that requires dynamic rounding.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/translate.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index cc81e77..0bd903c 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2196,6 +2196,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             /* MT_FPCR */
             va = load_fpr(ctx, ra);
             gen_helper_store_fpcr(cpu_env, va);
+            if (ctx->tb_rm == QUAL_RM_D) {
+                /* Re-do the copy of the rounding mode to fp_status
+                   the next time we use dynamic rounding.  */
+                ctx->tb_rm = -1;
+            }
             break;
         case 0x025:
             /* MF_FPCR */
-- 
1.9.3

[Qemu-devel] [PULL 02/18] target-alpha: Set PC correctly for floating-point exceptions

[Richard Henderson]

PC should be one past the faulting insn.  Add better commentary
for the machine-check exception path.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/helper.c     | 2 ++
 target-alpha/mem_helper.c | 9 ++++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 7c053a3..8d1df2d 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -527,6 +527,8 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
     env->error_code = error;
     if (retaddr) {
         cpu_restore_state(cs, retaddr);
+        /* Floating-point exceptions (our only users) point to the next PC.  */
+        env->pc += 4;
     }
     cpu_loop_exit(cs);
 }
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index fc4f57a..7b5e30d 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -128,7 +128,14 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 
     env->trap_arg0 = addr;
     env->trap_arg1 = is_write ? 1 : 0;
-    dynamic_excp(env, 0, EXCP_MCHK, 0);
+    cs->exception_index = EXCP_MCHK;
+    env->error_code = 0;
+
+    /* ??? We should cpu_restore_state to the faulting insn, but this hook
+       does not have access to the retaddr value from the orignal helper.
+       It's all moot until the QEMU PALcode grows an MCHK handler.  */
+
+    cpu_loop_exit(cs);
 }
 
 /* try to fill the TLB and return an exception if error. If retaddr is
-- 
1.9.3

[Qemu-devel] [PULL 03/18] target-alpha: Store IOV exception in fp_status

[Richard Henderson]

We were not representing the IOV (integer overflow) exception at all.
For ease of implementation, allocate a generic bit in softfloat, even
though softfloat will never raise the exception itself.

This can be licensed under either the softfloat-2a or -2b license.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 include/fpu/softfloat.h   | 13 +++++++------
 target-alpha/fpu_helper.c |  3 +++
 target-alpha/helper.c     |  6 ++++++
 3 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 77177c5..946fd3e 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -159,12 +159,13 @@ enum {
 | Software IEC/IEEE floating-point exception flags.
 *----------------------------------------------------------------------------*/
 enum {
-    float_flag_invalid   =  1,
-    float_flag_divbyzero =  4,
-    float_flag_overflow  =  8,
-    float_flag_underflow = 16,
-    float_flag_inexact   = 32,
-    float_flag_input_denormal = 64,
+    float_flag_invalid         = 1,
+    float_flag_int_overflow    = 2,
+    float_flag_divbyzero       = 4,
+    float_flag_overflow        = 8,
+    float_flag_underflow       = 16,
+    float_flag_inexact         = 32,
+    float_flag_input_denormal  = 64,
     float_flag_output_denormal = 128
 };
 
diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index d2d776c..aa83766 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -53,6 +53,9 @@ static inline void inline_fp_exc_raise(CPUAlphaState *env, uintptr_t retaddr,
         if (exc & float_flag_invalid) {
             hw_exc |= EXC_M_INV;
         }
+        if (exc & float_flag_int_overflow) {
+            hw_exc |= EXC_M_IOV;
+        }
         if (exc & float_flag_divbyzero) {
             hw_exc |= EXC_M_DZE;
         }
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 8d1df2d..6bcde21 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -36,6 +36,9 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env)
         if (t & float_flag_invalid) {
             r |= FPCR_INV;
         }
+        if (t & float_flag_int_overflow) {
+            r |= FPCR_IOV;
+        }
         if (t & float_flag_divbyzero) {
             r |= FPCR_DZE;
         }
@@ -103,6 +106,9 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
     if (val & FPCR_INV) {
         t |= float_flag_invalid;
     }
+    if (val & FPCR_IOV) {
+        t |= float_flag_int_overflow;
+    }
     if (val & FPCR_DZE) {
         t |= float_flag_divbyzero;
     }
-- 
1.9.3

[Qemu-devel] [PULL 04/18] target-alpha: Set fpcr_exc_status even for disabled exceptions

[Richard Henderson]

The qualifiers can suppress the raising of exceptions, but real
hardware still records that the exceptions occurred.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/fpu_helper.c | 67 ++++++++++++++++++++++++++---------------------
 target-alpha/translate.c  | 41 ++++++++++-------------------
 2 files changed, 51 insertions(+), 57 deletions(-)

diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index aa83766..efc5dfa 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -44,50 +44,57 @@ uint32_t helper_fp_exc_get(CPUAlphaState *env)
     return get_float_exception_flags(&FP_STATUS);
 }
 
-static inline void inline_fp_exc_raise(CPUAlphaState *env, uintptr_t retaddr,
-                                       uint32_t exc, uint32_t regno)
+static inline void fp_exc_raise1(CPUAlphaState *env, uintptr_t retaddr,
+                                 uint32_t exc, uint32_t regno)
 {
-    if (exc) {
-        uint32_t hw_exc = 0;
-
-        if (exc & float_flag_invalid) {
-            hw_exc |= EXC_M_INV;
-        }
-        if (exc & float_flag_int_overflow) {
-            hw_exc |= EXC_M_IOV;
-        }
-        if (exc & float_flag_divbyzero) {
-            hw_exc |= EXC_M_DZE;
-        }
-        if (exc & float_flag_overflow) {
-            hw_exc |= EXC_M_FOV;
-        }
-        if (exc & float_flag_underflow) {
-            hw_exc |= EXC_M_UNF;
-        }
-        if (exc & float_flag_inexact) {
-            hw_exc |= EXC_M_INE;
-        }
-
-        arith_excp(env, retaddr, hw_exc, 1ull << regno);
+    uint32_t hw_exc = 0;
+    if (exc & float_flag_invalid) {
+        hw_exc |= EXC_M_INV;
+    }
+    if (exc & float_flag_int_overflow) {
+        hw_exc |= EXC_M_IOV;
     }
+    if (exc & float_flag_divbyzero) {
+        hw_exc |= EXC_M_DZE;
+    }
+    if (exc & float_flag_overflow) {
+        hw_exc |= EXC_M_FOV;
+    }
+    if (exc & float_flag_underflow) {
+        hw_exc |= EXC_M_UNF;
+    }
+    if (exc & float_flag_inexact) {
+        hw_exc |= EXC_M_INE;
+    }
+    arith_excp(env, retaddr, hw_exc, 1ull << regno);
 }
 
 /* Raise exceptions for ieee fp insns without software completion.
    In that case there are no exceptions that don't trap; the mask
    doesn't apply.  */
-void helper_fp_exc_raise(CPUAlphaState *env, uint32_t exc, uint32_t regno)
+void helper_fp_exc_raise(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
 {
-    inline_fp_exc_raise(env, GETPC(), exc, regno);
+    uint32_t exc = (uint8_t)env->fp_status.float_exception_flags;
+    if (exc) {
+        env->fpcr_exc_status |= exc;
+        exc &= ~ignore;
+        if (exc) {
+            fp_exc_raise1(env, GETPC(), exc, regno, 0);
+        }
+    }
 }
 
 /* Raise exceptions for ieee fp insns with software completion.  */
-void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t exc, uint32_t regno)
+void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
 {
+    uint32_t exc = (uint8_t)env->fp_status.float_exception_flags;
     if (exc) {
         env->fpcr_exc_status |= exc;
-        exc &= ~env->fpcr_exc_mask;
-        inline_fp_exc_raise(env, GETPC(), exc, regno);
+        exc &= ~ignore;
+        if (exc) {
+            exc &= ~env->fpcr_exc_mask;
+            fp_exc_raise1(env, GETPC(), exc, regno);
+        }
     }
 }
 
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 0bd903c..1c2d72e 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -672,26 +672,24 @@ static void gen_fp_exc_clear(void)
 #endif
 }
 
-static void gen_fp_exc_raise_ignore(int rc, int fn11, int ignore)
+static void gen_fp_exc_raise(int rc, int fn11)
 {
     /* ??? We ought to be able to do something with imprecise exceptions.
        E.g. notice we're still in the trap shadow of something within the
        TB and do not generate the code to signal the exception; end the TB
        when an exception is forced to arrive, either by consumption of a
        register value or TRAPB or EXCB.  */
-    TCGv_i32 exc = tcg_temp_new_i32();
-    TCGv_i32 reg;
+    TCGv_i32 reg, ign;
+    uint32_t ignore = 0;
 
-#if defined(CONFIG_SOFTFLOAT_INLINE)
-    tcg_gen_ld8u_i32(exc, cpu_env,
-                     offsetof(CPUAlphaState, fp_status.float_exception_flags));
-#else
-    gen_helper_fp_exc_get(exc, cpu_env);
-#endif
-
-    if (ignore) {
-        tcg_gen_andi_i32(exc, exc, ~ignore);
+    if (!(fn11 & QUAL_U)) {
+        /* Note that QUAL_U == QUAL_V, so ignore either.  */
+        ignore |= float_flag_underflow | float_flag_int_overflow;
+    }
+    if (!(fn11 & QUAL_I)) {
+        ignore |= float_flag_inexact;
     }
+    ign = tcg_const_i32(ignore);
 
     /* ??? Pass in the regno of the destination so that the helper can
        set EXC_MASK, which contains a bitmask of destination registers
@@ -699,20 +697,14 @@ static void gen_fp_exc_raise_ignore(int rc, int fn11, int ignore)
        does not require this.  We do need it for a guest kernel's entArith,
        or if we were to do something clever with imprecise exceptions.  */
     reg = tcg_const_i32(rc + 32);
-
     if (fn11 & QUAL_S) {
-        gen_helper_fp_exc_raise_s(cpu_env, exc, reg);
+        gen_helper_fp_exc_raise_s(cpu_env, ign, reg);
     } else {
-        gen_helper_fp_exc_raise(cpu_env, exc, reg);
+        gen_helper_fp_exc_raise(cpu_env, ign, reg);
     }
 
     tcg_temp_free_i32(reg);
-    tcg_temp_free_i32(exc);
-}
-
-static inline void gen_fp_exc_raise(int rc, int fn11)
-{
-    gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);
+    tcg_temp_free_i32(ign);
 }
 
 static void gen_fcvtlq(TCGv vc, TCGv vb)
@@ -773,7 +765,6 @@ IEEE_ARITH2(cvtts)
 static void gen_fcvttq(DisasContext *ctx, int rb, int rc, int fn11)
 {
     TCGv vb, vc;
-    int ignore = 0;
 
     /* No need to set flushzero, since we have an integer output.  */
     gen_fp_exc_clear();
@@ -788,20 +779,16 @@ static void gen_fcvttq(DisasContext *ctx, int rb, int rc, int fn11)
         break;
     case QUAL_V | QUAL_RM_C:
     case QUAL_S | QUAL_V | QUAL_RM_C:
-        ignore = float_flag_inexact;
-        /* FALLTHRU */
     case QUAL_S | QUAL_V | QUAL_I | QUAL_RM_C:
         gen_helper_cvttq_svic(vc, cpu_env, vb);
         break;
     default:
         gen_qual_roundmode(ctx, fn11);
         gen_helper_cvttq(vc, cpu_env, vb);
-        ignore |= (fn11 & QUAL_V ? 0 : float_flag_overflow);
-        ignore |= (fn11 & QUAL_I ? 0 : float_flag_inexact);
         break;
     }
 
-    gen_fp_exc_raise_ignore(rc, fn11, ignore);
+    gen_fp_exc_raise(rc, fn11);
 }
 
 static void gen_ieee_intcvt(DisasContext *ctx,
-- 
1.9.3

[Qemu-devel] [PULL 05/18] target-alpha: Set EXC_M_SWC for exceptions from /S insns

[Richard Henderson]

Previously forgotten, the kernel needs the software completion bit to
know that it needs to emulate software completion qualified insns.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/fpu_helper.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index efc5dfa..8bd4c08 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -45,9 +45,8 @@ uint32_t helper_fp_exc_get(CPUAlphaState *env)
 }
 
 static inline void fp_exc_raise1(CPUAlphaState *env, uintptr_t retaddr,
-                                 uint32_t exc, uint32_t regno)
+                                 uint32_t exc, uint32_t regno, uint32_t hw_exc)
 {
-    uint32_t hw_exc = 0;
     if (exc & float_flag_invalid) {
         hw_exc |= EXC_M_INV;
     }
@@ -93,7 +92,7 @@ void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
         exc &= ~ignore;
         if (exc) {
             exc &= ~env->fpcr_exc_mask;
-            fp_exc_raise1(env, GETPC(), exc, regno);
+            fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC);
         }
     }
 }
-- 
1.9.3

[Qemu-devel] [PULL 06/18] target-alpha: Raise IOV from CVTTQ

[Richard Henderson]

Floating-point overflow is a different bit from integer overflow.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/fpu_helper.c | 25 ++++++++++---------------
 target-alpha/helper.h     |  1 -
 target-alpha/translate.c  | 17 ++++-------------
 3 files changed, 14 insertions(+), 29 deletions(-)

diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index 8bd4c08..19f3ebc 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -693,12 +693,10 @@ uint64_t helper_cvtqs(CPUAlphaState *env, uint64_t a)
 
 /* Implement float64 to uint64 conversion without saturation -- we must
    supply the truncated result.  This behaviour is used by the compiler
-   to get unsigned conversion for free with the same instruction.
-
-   The VI flag is set when overflow or inexact exceptions should be raised.  */
+   to get unsigned conversion for free with the same instruction.  */
 
 static inline uint64_t inline_cvttq(CPUAlphaState *env, uint64_t a,
-                                    int roundmode, int VI)
+                                    int roundmode)
 {
     uint64_t frac, ret = 0;
     uint32_t exp, sign, exc = 0;
@@ -713,7 +711,8 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env, uint64_t a,
             goto do_underflow;
         }
     } else if (exp == 0x7ff) {
-        exc = (frac ? float_flag_invalid : VI ? float_flag_overflow : 0);
+        exc = (frac ? float_flag_invalid
+               : float_flag_int_overflow | float_flag_inexact);
     } else {
         /* Restore implicit bit.  */
         frac |= 0x10000000000000ull;
@@ -722,10 +721,11 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env, uint64_t a,
         if (shift >= 0) {
             /* In this case the number is so large that we must shift
                the fraction left.  There is no rounding to do.  */
+            exc = float_flag_int_overflow | float_flag_inexact;
             if (shift < 63) {
                 ret = frac << shift;
-                if (VI && (ret >> shift) != frac) {
-                    exc = float_flag_overflow;
+                if ((ret >> shift) == frac) {
+                    exc = 0;
                 }
             }
         } else {
@@ -748,7 +748,7 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env, uint64_t a,
             }
 
             if (round) {
-                exc = (VI ? float_flag_inexact : 0);
+                exc = float_flag_inexact;
                 switch (roundmode) {
                 case float_round_nearest_even:
                     if (round == (1ull << 63)) {
@@ -782,17 +782,12 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env, uint64_t a,
 
 uint64_t helper_cvttq(CPUAlphaState *env, uint64_t a)
 {
-    return inline_cvttq(env, a, FP_STATUS.float_rounding_mode, 1);
+    return inline_cvttq(env, a, FP_STATUS.float_rounding_mode);
 }
 
 uint64_t helper_cvttq_c(CPUAlphaState *env, uint64_t a)
 {
-    return inline_cvttq(env, a, float_round_to_zero, 0);
-}
-
-uint64_t helper_cvttq_svic(CPUAlphaState *env, uint64_t a)
-{
-    return inline_cvttq(env, a, float_round_to_zero, 1);
+    return inline_cvttq(env, a, float_round_to_zero);
 }
 
 uint64_t helper_cvtqt(CPUAlphaState *env, uint64_t a)
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index a451cfe..173db01 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -83,7 +83,6 @@ DEF_HELPER_FLAGS_2(cvtqg, TCG_CALL_NO_RWG, i64, env, i64)
 
 DEF_HELPER_FLAGS_2(cvttq, TCG_CALL_NO_RWG, i64, env, i64)
 DEF_HELPER_FLAGS_2(cvttq_c, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(cvttq_svic, TCG_CALL_NO_RWG, i64, env, i64)
 
 DEF_HELPER_FLAGS_2(setroundmode, TCG_CALL_NO_RWG, void, env, i32)
 DEF_HELPER_FLAGS_2(setflushzero, TCG_CALL_NO_RWG, void, env, i32)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 1c2d72e..183573d 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -771,23 +771,14 @@ static void gen_fcvttq(DisasContext *ctx, int rb, int rc, int fn11)
     vb = gen_ieee_input(ctx, rb, fn11, 0);
     vc = dest_fpr(ctx, rc);
 
-    /* Almost all integer conversions use cropped rounding, and most
-       also do not have integer overflow enabled.  Special case that.  */
-    switch (fn11) {
-    case QUAL_RM_C:
+    /* Almost all integer conversions use cropped rounding;
+       special case that.  */
+    if ((fn11 & QUAL_RM_MASK) == QUAL_RM_C) {
         gen_helper_cvttq_c(vc, cpu_env, vb);
-        break;
-    case QUAL_V | QUAL_RM_C:
-    case QUAL_S | QUAL_V | QUAL_RM_C:
-    case QUAL_S | QUAL_V | QUAL_I | QUAL_RM_C:
-        gen_helper_cvttq_svic(vc, cpu_env, vb);
-        break;
-    default:
+    } else {
         gen_qual_roundmode(ctx, fn11);
         gen_helper_cvttq(vc, cpu_env, vb);
-        break;
     }
-
     gen_fp_exc_raise(rc, fn11);
 }
 
-- 
1.9.3

[Qemu-devel] [PULL 07/18] target-alpha: Fix cvttq vs large integers

[Richard Henderson]

The range +- 2**63 - 2**64 was returning the wrong truncated
result.  We also incorrectly signaled overflow for -2**63.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/fpu_helper.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index 19f3ebc..2b6c96b 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -721,12 +721,12 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env, uint64_t a,
         if (shift >= 0) {
             /* In this case the number is so large that we must shift
                the fraction left.  There is no rounding to do.  */
-            exc = float_flag_int_overflow | float_flag_inexact;
-            if (shift < 63) {
+            if (shift < 64) {
                 ret = frac << shift;
-                if ((ret >> shift) == frac) {
-                    exc = 0;
-                }
+            }
+            /* Check for overflow.  Note the special case of -0x1p63.  */
+            if (shift >= 11 && a != 0xC3E0000000000000ull) {
+                exc = float_flag_int_overflow | float_flag_inexact;
             }
         } else {
             uint64_t round;
-- 
1.9.3

[Qemu-devel] [PULL 08/18] target-alpha: Fix cvttq vs inf

[Richard Henderson]

We should raise INV for infinities as well, not OVR+INE.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/fpu_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index 2b6c96b..9b297de 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -711,8 +711,7 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env, uint64_t a,
             goto do_underflow;
         }
     } else if (exp == 0x7ff) {
-        exc = (frac ? float_flag_invalid
-               : float_flag_int_overflow | float_flag_inexact);
+        exc = float_flag_invalid;
     } else {
         /* Restore implicit bit.  */
         frac |= 0x10000000000000ull;
-- 
1.9.3

[Qemu-devel] [PULL 09/18] target-alpha: Fix integer overflow checking insns

[Richard Henderson]

We need to write the result to the destination register before
raising any exception.  Thus inline the code for each insn, and
check for any exception after we're done.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/helper.h     |  7 +-----
 target-alpha/int_helper.c | 59 ++--------------------------------------------
 target-alpha/translate.c  | 60 +++++++++++++++++++++++++++++++++++++++++------
 3 files changed, 56 insertions(+), 70 deletions(-)

diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 173db01..2cc100b 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -1,12 +1,7 @@
 DEF_HELPER_3(excp, noreturn, env, int, int)
 DEF_HELPER_FLAGS_1(load_pcc, TCG_CALL_NO_RWG_SE, i64, env)
 
-DEF_HELPER_FLAGS_3(addqv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(addlv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(subqv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(sublv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(mullv, TCG_CALL_NO_WG, i64, env, i64, i64)
-DEF_HELPER_FLAGS_3(mulqv, TCG_CALL_NO_WG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(check_overflow, TCG_CALL_NO_WG, void, env, i64, i64)
 
 DEF_HELPER_FLAGS_1(ctpop, TCG_CALL_NO_RWG_SE, i64, i64)
 DEF_HELPER_FLAGS_1(ctlz, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target-alpha/int_helper.c b/target-alpha/int_helper.c
index 7a205eb..8e4537f 100644
--- a/target-alpha/int_helper.c
+++ b/target-alpha/int_helper.c
@@ -249,64 +249,9 @@ uint64_t helper_unpkbw(uint64_t op1)
             | ((op1 & 0xff000000) << 24));
 }
 
-uint64_t helper_addqv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
+void helper_check_overflow(CPUAlphaState *env, uint64_t op1, uint64_t op2)
 {
-    uint64_t tmp = op1;
-    op1 += op2;
-    if (unlikely((tmp ^ op2 ^ (-1ULL)) & (tmp ^ op1) & (1ULL << 63))) {
+    if (unlikely(op1 != op2)) {
         arith_excp(env, GETPC(), EXC_M_IOV, 0);
     }
-    return op1;
-}
-
-uint64_t helper_addlv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
-    uint64_t tmp = op1;
-    op1 = (uint32_t)(op1 + op2);
-    if (unlikely((tmp ^ op2 ^ (-1UL)) & (tmp ^ op1) & (1UL << 31))) {
-        arith_excp(env, GETPC(), EXC_M_IOV, 0);
-    }
-    return op1;
-}
-
-uint64_t helper_subqv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
-    uint64_t res;
-    res = op1 - op2;
-    if (unlikely((op1 ^ op2) & (res ^ op1) & (1ULL << 63))) {
-        arith_excp(env, GETPC(), EXC_M_IOV, 0);
-    }
-    return res;
-}
-
-uint64_t helper_sublv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
-    uint32_t res;
-    res = op1 - op2;
-    if (unlikely((op1 ^ op2) & (res ^ op1) & (1UL << 31))) {
-        arith_excp(env, GETPC(), EXC_M_IOV, 0);
-    }
-    return res;
-}
-
-uint64_t helper_mullv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
-    int64_t res = (int64_t)op1 * (int64_t)op2;
-
-    if (unlikely((int32_t)res != res)) {
-        arith_excp(env, GETPC(), EXC_M_IOV, 0);
-    }
-    return (int64_t)((int32_t)res);
-}
-
-uint64_t helper_mulqv(CPUAlphaState *env, uint64_t op1, uint64_t op2)
-{
-    uint64_t tl, th;
-
-    muls64(&tl, &th, op1, op2);
-    /* If th != 0 && th != -1, then we had an overflow */
-    if (unlikely((th + 1) > 1)) {
-        arith_excp(env, GETPC(), EXC_M_IOV, 0);
-    }
-    return tl;
 }
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 183573d..6ea33f3 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1377,7 +1377,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
     uint16_t fn11;
     uint8_t opc, ra, rb, rc, fpfn, fn7, lit;
     bool islit;
-    TCGv va, vb, vc, tmp;
+    TCGv va, vb, vc, tmp, tmp2;
     TCGv_i32 t32;
     ExitStatus ret;
 
@@ -1589,11 +1589,23 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             break;
         case 0x40:
             /* ADDL/V */
-            gen_helper_addlv(vc, cpu_env, va, vb);
+            tmp = tcg_temp_new();
+            tcg_gen_ext32s_i64(tmp, va);
+            tcg_gen_ext32s_i64(vc, vb);
+            tcg_gen_add_i64(tmp, tmp, vc);
+            tcg_gen_ext32s_i64(vc, tmp);
+            gen_helper_check_overflow(cpu_env, vc, tmp);
+            tcg_temp_free(tmp);
             break;
         case 0x49:
             /* SUBL/V */
-            gen_helper_sublv(vc, cpu_env, va, vb);
+            tmp = tcg_temp_new();
+            tcg_gen_ext32s_i64(tmp, va);
+            tcg_gen_ext32s_i64(vc, vb);
+            tcg_gen_sub_i64(tmp, tmp, vc);
+            tcg_gen_ext32s_i64(vc, tmp);
+            gen_helper_check_overflow(cpu_env, vc, tmp);
+            tcg_temp_free(tmp);
             break;
         case 0x4D:
             /* CMPLT */
@@ -1601,11 +1613,33 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             break;
         case 0x60:
             /* ADDQ/V */
-            gen_helper_addqv(vc, cpu_env, va, vb);
+            tmp = tcg_temp_new();
+            tmp2 = tcg_temp_new();
+            tcg_gen_eqv_i64(tmp, va, vb);
+            tcg_gen_mov_i64(tmp2, va);
+            tcg_gen_add_i64(vc, va, vb);
+            tcg_gen_xor_i64(tmp2, tmp2, vc);
+            tcg_gen_and_i64(tmp, tmp, tmp2);
+            tcg_gen_shri_i64(tmp, tmp, 63);
+            tcg_gen_movi_i64(tmp2, 0);
+            gen_helper_check_overflow(cpu_env, tmp, tmp2);
+            tcg_temp_free(tmp);
+            tcg_temp_free(tmp2);
             break;
         case 0x69:
             /* SUBQ/V */
-            gen_helper_subqv(vc, cpu_env, va, vb);
+            tmp = tcg_temp_new();
+            tmp2 = tcg_temp_new();
+            tcg_gen_xor_i64(tmp, va, vb);
+            tcg_gen_mov_i64(tmp2, va);
+            tcg_gen_sub_i64(vc, va, vb);
+            tcg_gen_xor_i64(tmp2, tmp2, vc);
+            tcg_gen_and_i64(tmp, tmp, tmp2);
+            tcg_gen_shri_i64(tmp, tmp, 63);
+            tcg_gen_movi_i64(tmp2, 0);
+            gen_helper_check_overflow(cpu_env, tmp, tmp2);
+            tcg_temp_free(tmp);
+            tcg_temp_free(tmp2);
             break;
         case 0x6D:
             /* CMPLE */
@@ -1900,11 +1934,23 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             break;
         case 0x40:
             /* MULL/V */
-            gen_helper_mullv(vc, cpu_env, va, vb);
+            tmp = tcg_temp_new();
+            tcg_gen_ext32s_i64(tmp, va);
+            tcg_gen_ext32s_i64(vc, vb);
+            tcg_gen_mul_i64(tmp, tmp, vc);
+            tcg_gen_ext32s_i64(vc, tmp);
+            gen_helper_check_overflow(cpu_env, vc, tmp);
+            tcg_temp_free(tmp);
             break;
         case 0x60:
             /* MULQ/V */
-            gen_helper_mulqv(vc, cpu_env, va, vb);
+            tmp = tcg_temp_new();
+            tmp2 = tcg_temp_new();
+            tcg_gen_muls2_i64(vc, tmp, va, vb);
+            tcg_gen_sari_i64(tmp2, vc, 63);
+            gen_helper_check_overflow(cpu_env, tmp, tmp2);
+            tcg_temp_free(tmp);
+            tcg_temp_free(tmp2);
             break;
         default:
             goto invalid_opc;
-- 
1.9.3

[Qemu-devel] [PULL 10/18] target-alpha: Implement WH64EN

[Richard Henderson]

Backward compatible cache insn introduced for EV7.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/translate.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 6ea33f3..e0fc0a3 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2333,6 +2333,10 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             /* WH64 */
             /* No-op */
             break;
+        case 0xFC00:
+            /* WH64EN */
+            /* No-op */
+            break;
         default:
             goto invalid_opc;
         }
-- 
1.9.3

[Qemu-devel] [PULL 11/18] target-alpha: Disallow literal operand to 1C.30 to 1C.37

[Richard Henderson]

Before 64f45e49 we used to have literal checks for 4 of these 8 opcodes.
Confirmed that real hardware doesn't allow them.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/translate.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index e0fc0a3..5785dd7 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1357,6 +1357,13 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
 }
 #endif /* !USER_ONLY*/
 
+#define REQUIRE_NO_LIT                          \
+    do {                                        \
+        if (real_islit) {                       \
+            goto invalid_opc;                   \
+        }                                       \
+    } while (0)
+
 #define REQUIRE_TB_FLAG(FLAG)                   \
     do {                                        \
         if ((ctx->tb->flags & (FLAG)) == 0) {   \
@@ -1376,7 +1383,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
     int32_t disp21, disp16, disp12 __attribute__((unused));
     uint16_t fn11;
     uint8_t opc, ra, rb, rc, fpfn, fn7, lit;
-    bool islit;
+    bool islit, real_islit;
     TCGv va, vb, vc, tmp, tmp2;
     TCGv_i32 t32;
     ExitStatus ret;
@@ -1386,7 +1393,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
     ra = extract32(insn, 21, 5);
     rb = extract32(insn, 16, 5);
     rc = extract32(insn, 0, 5);
-    islit = extract32(insn, 12, 1);
+    real_islit = islit = extract32(insn, 12, 1);
     lit = extract32(insn, 13, 8);
 
     disp21 = sextract32(insn, 0, 21);
@@ -2481,11 +2488,13 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             /* CTPOP */
             REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);
             REQUIRE_REG_31(ra);
+            REQUIRE_NO_LIT;
             gen_helper_ctpop(vc, vb);
             break;
         case 0x31:
             /* PERR */
             REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
+            REQUIRE_NO_LIT;
             va = load_gpr(ctx, ra);
             gen_helper_perr(vc, va, vb);
             break;
@@ -2493,36 +2502,42 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             /* CTLZ */
             REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);
             REQUIRE_REG_31(ra);
+            REQUIRE_NO_LIT;
             gen_helper_ctlz(vc, vb);
             break;
         case 0x33:
             /* CTTZ */
             REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);
             REQUIRE_REG_31(ra);
+            REQUIRE_NO_LIT;
             gen_helper_cttz(vc, vb);
             break;
         case 0x34:
             /* UNPKBW */
             REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
             REQUIRE_REG_31(ra);
+            REQUIRE_NO_LIT;
             gen_helper_unpkbw(vc, vb);
             break;
         case 0x35:
             /* UNPKBL */
             REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
             REQUIRE_REG_31(ra);
+            REQUIRE_NO_LIT;
             gen_helper_unpkbl(vc, vb);
             break;
         case 0x36:
             /* PKWB */
             REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
             REQUIRE_REG_31(ra);
+            REQUIRE_NO_LIT;
             gen_helper_pkwb(vc, vb);
             break;
         case 0x37:
             /* PKLB */
             REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
             REQUIRE_REG_31(ra);
+            REQUIRE_NO_LIT;
             gen_helper_pklb(vc, vb);
             break;
         case 0x38:
-- 
1.9.3

[Qemu-devel] [PULL 12/18] target-alpha: Ignore the unused fp_status exceptions

[Richard Henderson]

Mask out the exceptions that have no correspondance on
Alpha so that zero/non-zero tests work as expected.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/fpu_helper.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index 9b297de..f7fe31e 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -68,12 +68,17 @@ static inline void fp_exc_raise1(CPUAlphaState *env, uintptr_t retaddr,
     arith_excp(env, retaddr, hw_exc, 1ull << regno);
 }
 
+/* There are several flags that softfloat raises that are irrelevant.  */
+#define EXC_MASK (float_flag_invalid | float_flag_int_overflow \
+                  | float_flag_divbyzero | float_flag_overflow \
+                  | float_flag_underflow | float_flag_inexact)
+
 /* Raise exceptions for ieee fp insns without software completion.
    In that case there are no exceptions that don't trap; the mask
    doesn't apply.  */
 void helper_fp_exc_raise(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
 {
-    uint32_t exc = (uint8_t)env->fp_status.float_exception_flags;
+    uint32_t exc = env->fp_status.float_exception_flags & EXC_MASK;
     if (exc) {
         env->fpcr_exc_status |= exc;
         exc &= ~ignore;
@@ -86,7 +91,7 @@ void helper_fp_exc_raise(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
 /* Raise exceptions for ieee fp insns with software completion.  */
 void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
 {
-    uint32_t exc = (uint8_t)env->fp_status.float_exception_flags;
+    uint32_t exc = env->fp_status.float_exception_flags & EXC_MASK;
     if (exc) {
         env->fpcr_exc_status |= exc;
         exc &= ~ignore;
-- 
1.9.3

[Qemu-devel] [PULL 13/18] target-alpha: Raise EXC_M_INV properly for fp inputs

[Richard Henderson]

Ignore DNZ if software completion isn't used.  Raise INV for
denormals in system mode so the OS completion handler sees them.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/fpu_helper.c | 33 +++++++++++++++++++++++----------
 target-alpha/helper.h     |  1 +
 target-alpha/translate.c  |  7 +++++++
 3 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index f7fe31e..cf6c44a 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -110,16 +110,14 @@ void helper_ieee_input(CPUAlphaState *env, uint64_t val)
     uint64_t frac = val & 0xfffffffffffffull;
 
     if (exp == 0) {
-        /* Denormals without DNZ set raise an exception.  */
-        if (frac != 0 && !env->fp_status.flush_inputs_to_zero) {
-            arith_excp(env, GETPC(), EXC_M_UNF, 0);
+        /* Denormals without /S raise an exception.  */
+        if (frac != 0) {
+            arith_excp(env, GETPC(), EXC_M_INV, 0);
         }
     } else if (exp == 0x7ff) {
         /* Infinity or NaN.  */
-        /* ??? I'm not sure these exception bit flags are correct.  I do
-           know that the Linux kernel, at least, doesn't rely on them and
-           just emulates the insn to figure out what exception to use.  */
-        arith_excp(env, GETPC(), frac ? EXC_M_INV : EXC_M_FOV, 0);
+        env->fpcr_exc_status |= float_flag_invalid;
+        arith_excp(env, GETPC(), EXC_M_INV, 0);
     }
 }
 
@@ -130,16 +128,31 @@ void helper_ieee_input_cmp(CPUAlphaState *env, uint64_t val)
     uint64_t frac = val & 0xfffffffffffffull;
 
     if (exp == 0) {
-        /* Denormals without DNZ set raise an exception.  */
-        if (frac != 0 && !env->fp_status.flush_inputs_to_zero) {
-            arith_excp(env, GETPC(), EXC_M_UNF, 0);
+        /* Denormals without /S raise an exception.  */
+        if (frac != 0) {
+            arith_excp(env, GETPC(), EXC_M_INV, 0);
         }
     } else if (exp == 0x7ff && frac) {
         /* NaN.  */
+        env->fpcr_exc_status |= float_flag_invalid;
         arith_excp(env, GETPC(), EXC_M_INV, 0);
     }
 }
 
+/* Input handing with software completion.  Trap for denorms, unless DNZ
+   is set.  If we try to support DNOD (which none of the produced hardware
+   did, AFAICS), we'll need to suppress the trap when FPCR.DNOD is set;
+   then the code downstream of that will need to cope with denorms sans
+   flush_input_to_zero.  Most of it should work sanely, but there's
+   nothing to compare with.  */
+void helper_ieee_input_s(CPUAlphaState *env, uint64_t val)
+{
+    if (unlikely(2 * val - 1 < 0x1fffffffffffffull)
+        && !env->fp_status.flush_inputs_to_zero) {
+        arith_excp(env, GETPC(), EXC_M_INV | EXC_M_SWC, 0);
+    }
+}
+
 /* F floating (VAX) */
 static uint64_t float32_to_f(float32 fa)
 {
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 2cc100b..596f24d 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -88,6 +88,7 @@ DEF_HELPER_FLAGS_3(fp_exc_raise_s, TCG_CALL_NO_WG, void, env, i32, i32)
 
 DEF_HELPER_FLAGS_2(ieee_input, TCG_CALL_NO_WG, void, env, i64)
 DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
+DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64)
 DEF_HELPER_FLAGS_2(fcvtql_v_input, TCG_CALL_NO_WG, void, env, i64)
 
 #if !defined (CONFIG_USER_ONLY)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 5785dd7..3a7c2ba 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -655,6 +655,13 @@ static TCGv gen_ieee_input(DisasContext *ctx, int reg, int fn11, int is_cmp)
             } else {
                 gen_helper_ieee_input(cpu_env, val);
             }
+        } else {
+#ifndef CONFIG_USER_ONLY
+            /* In system mode, raise exceptions for denormals like real
+               hardware.  In user mode, proceed as if the OS completion
+               handler is handling the denormal as per spec.  */
+            gen_helper_ieee_input_s(cpu_env, val);
+#endif
         }
     }
     return val;
-- 
1.9.3

[Qemu-devel] [PULL 14/18] target-alpha: Suppress underflow from CVTTQ if DNZ

[Richard Henderson]

I.e. respect flush_inputs_to_zero.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/fpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index cf6c44a..796d907 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -725,7 +725,7 @@ static inline uint64_t inline_cvttq(CPUAlphaState *env, uint64_t a,
     frac = a & 0xfffffffffffffull;
 
     if (exp == 0) {
-        if (unlikely(frac != 0)) {
+        if (unlikely(frac != 0) && !env->fp_status.flush_inputs_to_zero) {
             goto do_underflow;
         }
     } else if (exp == 0x7ff) {
-- 
1.9.3

[Qemu-devel] [PULL 15/18] target-alpha: Raise IOV from CVTQL

[Richard Henderson]

Even if an exception isn't taken, the status flags need updating
and the result should be written to the destination.  Move the body
of cvtql out of line, since we now always need a call.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/fpu_helper.c |  8 ++++++--
 target-alpha/helper.h     |  3 ++-
 target-alpha/translate.c  | 34 +++++-----------------------------
 3 files changed, 13 insertions(+), 32 deletions(-)

diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index 796d907..67d9a5b 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -842,9 +842,13 @@ uint64_t helper_cvtqg(CPUAlphaState *env, uint64_t a)
     return float64_to_g(fr);
 }
 
-void helper_fcvtql_v_input(CPUAlphaState *env, uint64_t val)
+uint64_t helper_cvtql(CPUAlphaState *env, uint64_t val)
 {
+    int exc = 0;
     if (val != (int32_t)val) {
-        arith_excp(env, GETPC(), EXC_M_IOV, 0);
+        exc = float_flag_int_overflow | float_flag_inexact;
     }
+    set_float_exception_flags(exc, &FP_STATUS);
+
+    return ((val & 0xc0000000) << 32) | ((val & 0x3fffffff) << 29);
 }
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 596f24d..128f7a1 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -79,6 +79,8 @@ DEF_HELPER_FLAGS_2(cvtqg, TCG_CALL_NO_RWG, i64, env, i64)
 DEF_HELPER_FLAGS_2(cvttq, TCG_CALL_NO_RWG, i64, env, i64)
 DEF_HELPER_FLAGS_2(cvttq_c, TCG_CALL_NO_RWG, i64, env, i64)
 
+DEF_HELPER_FLAGS_2(cvtql, TCG_CALL_NO_RWG, i64, env, i64)
+
 DEF_HELPER_FLAGS_2(setroundmode, TCG_CALL_NO_RWG, void, env, i32)
 DEF_HELPER_FLAGS_2(setflushzero, TCG_CALL_NO_RWG, void, env, i32)
 DEF_HELPER_FLAGS_1(fp_exc_clear, TCG_CALL_NO_RWG, void, env)
@@ -89,7 +91,6 @@ DEF_HELPER_FLAGS_3(fp_exc_raise_s, TCG_CALL_NO_WG, void, env, i32, i32)
 DEF_HELPER_FLAGS_2(ieee_input, TCG_CALL_NO_WG, void, env, i64)
 DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
 DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64)
-DEF_HELPER_FLAGS_2(fcvtql_v_input, TCG_CALL_NO_WG, void, env, i64)
 
 #if !defined (CONFIG_USER_ONLY)
 DEF_HELPER_2(hw_ret, void, env, i64)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 3a7c2ba..8ad098a 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -729,19 +729,6 @@ static void gen_fcvtlq(TCGv vc, TCGv vb)
     tcg_temp_free(tmp);
 }
 
-static void gen_fcvtql(TCGv vc, TCGv vb)
-{
-    TCGv tmp = tcg_temp_new();
-
-    tcg_gen_andi_i64(tmp, vb, (int32_t)0xc0000000);
-    tcg_gen_andi_i64(vc, vb, 0x3FFFFFFF);
-    tcg_gen_shli_i64(tmp, tmp, 32);
-    tcg_gen_shli_i64(vc, vc, 29);
-    tcg_gen_or_i64(vc, vc, tmp);
-
-    tcg_temp_free(tmp);
-}
-
 static void gen_ieee_arith2(DisasContext *ctx,
                             void (*helper)(TCGv, TCGv_ptr, TCGv),
                             int rb, int rc, int fn11)
@@ -2269,25 +2256,14 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             /* FCMOVGT */
             gen_fcmov(ctx, TCG_COND_GT, ra, rb, rc);
             break;
-        case 0x030:
-            /* CVTQL */
-            REQUIRE_REG_31(ra);
-            vc = dest_fpr(ctx, rc);
-            vb = load_fpr(ctx, rb);
-            gen_fcvtql(vc, vb);
-            break;
-        case 0x130:
-            /* CVTQL/V */
-        case 0x530:
-            /* CVTQL/SV */
+        case 0x030: /* CVTQL */
+        case 0x130: /* CVTQL/V */
+        case 0x530: /* CVTQL/SV */
             REQUIRE_REG_31(ra);
-            /* ??? I'm pretty sure there's nothing that /sv needs to do that
-               /v doesn't do.  The only thing I can think is that /sv is a
-               valid instruction merely for completeness in the ISA.  */
             vc = dest_fpr(ctx, rc);
             vb = load_fpr(ctx, rb);
-            gen_helper_fcvtql_v_input(cpu_env, vb);
-            gen_fcvtql(vc, vb);
+            gen_helper_cvtql(vc, cpu_env, vb);
+            gen_fp_exc_raise(rc, fn11);
             break;
         default:
             goto invalid_opc;
-- 
1.9.3

[Qemu-devel] [PULL 16/18] target-alpha: Rename fcvtql

[Richard Henderson]

... to match the insn, which has no leading "f".

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 8ad098a..9129e44 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -714,7 +714,7 @@ static void gen_fp_exc_raise(int rc, int fn11)
     tcg_temp_free_i32(ign);
 }
 
-static void gen_fcvtlq(TCGv vc, TCGv vb)
+static void gen_cvtlq(TCGv vc, TCGv vb)
 {
     TCGv tmp = tcg_temp_new();
 
@@ -2185,7 +2185,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             REQUIRE_REG_31(ra);
             vc = dest_fpr(ctx, rc);
             vb = load_fpr(ctx, rb);
-            gen_fcvtlq(vc, vb);
+            gen_cvtlq(vc, vb);
             break;
         case 0x020:
             /* CPYS */
-- 
1.9.3

[Qemu-devel] [PULL 17/18] target-alpha: Fix fpcr_flush_to_zero initialization

[Richard Henderson]

The two bits required are UNDZ and UNFD, not UNDZ and DNOD.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 6bcde21..26d5188 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -159,8 +159,9 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
 
     env->fpcr_dnod = (val & FPCR_DNOD) != 0;
     env->fpcr_undz = (val & FPCR_UNDZ) != 0;
-    env->fpcr_flush_to_zero = env->fpcr_dnod & env->fpcr_undz;
     env->fp_status.flush_inputs_to_zero = (val & FPCR_DNZ) != 0;
+    env->fpcr_flush_to_zero
+      = (val & (FPCR_UNDZ | FPCR_UNFD)) == (FPCR_UNDZ | FPCR_UNFD);
 }
 
 uint64_t helper_load_fpcr(CPUAlphaState *env)
-- 
1.9.3

[Qemu-devel] [PULL 18/18] target-alpha: Remove DNOD bit from FPCR

[Richard Henderson]

It was never implemented, thus even for EV6 and EV7 the bit
is read-as-zero, writes-ignored.

Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/cpu.h    | 1 -
 target-alpha/helper.c | 8 +++-----
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index d9b861f..d3a6a4e 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -246,7 +246,6 @@ struct CPUAlphaState {
     uint8_t fpcr_exc_mask;
     uint8_t fpcr_dyn_round;
     uint8_t fpcr_flush_to_zero;
-    uint8_t fpcr_dnod;
     uint8_t fpcr_undz;
 
     /* The Internal Processor Registers.  Some of these we assume always
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 26d5188..d0b4964 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -88,19 +88,17 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env)
     if (env->fp_status.flush_inputs_to_zero) {
         r |= FPCR_DNZ;
     }
-    if (env->fpcr_dnod) {
-        r |= FPCR_DNOD;
-    }
     if (env->fpcr_undz) {
         r |= FPCR_UNDZ;
     }
+    /* DNOD was never implemented in hardware.  */
 
     return r;
 }
 
 void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
 {
-    uint8_t t;
+    int t;
 
     t = 0;
     if (val & FPCR_INV) {
@@ -157,11 +155,11 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
     }
     env->fpcr_dyn_round = t;
 
-    env->fpcr_dnod = (val & FPCR_DNOD) != 0;
     env->fpcr_undz = (val & FPCR_UNDZ) != 0;
     env->fp_status.flush_inputs_to_zero = (val & FPCR_DNZ) != 0;
     env->fpcr_flush_to_zero
       = (val & (FPCR_UNDZ | FPCR_UNFD)) == (FPCR_UNDZ | FPCR_UNFD);
+    /* DNOD was never implemented in hardware.  */
 }
 
 uint64_t helper_load_fpcr(CPUAlphaState *env)
-- 
1.9.3

Re: [Qemu-devel] [PULL 03/18] target-alpha: Store IOV exception in fp_status

[Peter Maydell]

On 9 July 2014 17:20, Richard Henderson <rth@twiddle.net> wrote:
> We were not representing the IOV (integer overflow) exception at all.
> For ease of implementation, allocate a generic bit in softfloat, even
> though softfloat will never raise the exception itself.

I don't think we should use softfloat flag bits for keeping
information which isn't about softfloat's status. Why can't
you just put this in the per-CPU state?

thanks
-- PMM

Re: [Qemu-devel] [PULL for-2.1 00/18] target-alpha patch queue

[Peter Maydell]

On 9 July 2014 17:20, Richard Henderson <rth@twiddle.net> wrote:
> The queue consists of Al Viro's recent work looking at the dark
> corner cases of Alpha FPU exception signalling, for which I am
> most grateful.
>
> Please pull for 2.1.

> Richard Henderson (18):

>  include/fpu/softfloat.h   |  13 ++--
>  target-alpha/cpu.h        |   1 -
>  target-alpha/fpu_helper.c | 139 +++++++++++++++++++--------------
>  target-alpha/helper.c     |  19 +++--
>  target-alpha/helper.h     |  12 +--
>  target-alpha/int_helper.c |  59 +-------------
>  target-alpha/mem_helper.c |   9 ++-
>  target-alpha/translate.c  | 191 +++++++++++++++++++++++++++-------------------
>  8 files changed, 227 insertions(+), 216 deletions(-)

My general feeling here is that this is too much code and too late
for 2.1; can we hold it over to 2.2 ?

thanks
-- PMM

Re: [Qemu-devel] [PULL for-2.1 00/18] target-alpha patch queue

[Richard Henderson]

On 07/09/2014 09:30 AM, Peter Maydell wrote:
> My general feeling here is that this is too much code and too late
> for 2.1; can we hold it over to 2.2 ?

Ok then.


r~

Re: [Qemu-devel] [PULL 03/18] target-alpha: Store IOV exception in fp_status

[Richard Henderson]

On 07/09/2014 09:28 AM, Peter Maydell wrote:
> I don't think we should use softfloat flag bits for keeping
> information which isn't about softfloat's status. Why can't
> you just put this in the per-CPU state?

It is (mostly) being stored in per-CPU state.  But for efficiency, the per-CPU
state is in the softfloat format.

For this new bit, I'd prefer to not require a second load to examine the
exception flags for the insn.  And while I could privately define a symbol for
the unused bit in the existing softfloat status, that seemed more hazardous
than just defining the bit in the global softfloat enumeration.


r~