From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44633) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X6izj-0001mD-Q4 for qemu-devel@nongnu.org; Mon, 14 Jul 2014 12:20:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X6izd-00083i-6O for qemu-devel@nongnu.org; Mon, 14 Jul 2014 12:20:51 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:14562) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X6izd-00083W-08 for qemu-devel@nongnu.org; Mon, 14 Jul 2014 12:20:45 -0400 From: Leon Alrae Date: Mon, 14 Jul 2014 17:19:55 +0100 Message-ID: <1405354795-25884-7-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1405354795-25884-1-git-send-email-leon.alrae@imgtec.com> References: <1405354795-25884-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 6/6] target-mips: enable features in MIPS64R6-generic CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 11 +++++++++-- 1 files changed, 9 insertions(+), 2 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index bcfc46a..0b70d05 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -519,7 +519,7 @@ static const mips_def_t mips_defs[] = }, { /* A generic CPU supporting MIPS64 Release 6 ISA. - FIXME: It does not support all the MIPS64R6 features yet. + FIXME: Support IEEE 754-2008 FP and misaligned memory accesses. Eventually this should be replaced by a real CPU model. */ .name = "MIPS64R6-generic", .CP0_PRid = 0x00010000, @@ -530,12 +530,19 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) | + (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M), + .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | + (3 << CP0C4_IE) | (1 << CP0C4_M), + .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x30D8FFFF, + .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask = 0, .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), -- 1.7.5.4