From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X6jGt-0004qG-GT for qemu-devel@nongnu.org; Mon, 14 Jul 2014 12:38:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X6jGm-00022V-7D for qemu-devel@nongnu.org; Mon, 14 Jul 2014 12:38:35 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:5035) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X6jGm-00021x-0Y for qemu-devel@nongnu.org; Mon, 14 Jul 2014 12:38:28 -0400 From: Bastian Koppelmann Date: Mon, 14 Jul 2014 18:41:05 +0100 Message-Id: <1405359671-25985-10-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1405359671-25985-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1405359671-25985-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v2 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Add instructions of SSRS and SLRO opcode format. Add micro-op generator functions for offset loads. Signed-off-by: Bastian Koppelmann --- v1 -> v2: - Replace OP_MEM_INDIRECT with gen_offset_ld/st functions using TCGMemOp. - Change load/store instructions to use TCGMemOp. target-tricore/translate.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 4206a8a..5773b59 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -98,6 +98,26 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, /* * Functions to generate micro-ops */ + +/* Functions for load/save to/from memory */ +static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, + int16_t con, TCGMemOp mop) +{ + TCGv temp = tcg_temp_new(); + tcg_gen_addi_tl(temp, r2, con); + tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); + tcg_temp_free(temp); +} + +static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, + int16_t con, TCGMemOp mop) +{ + TCGv temp = tcg_temp_new(); + tcg_gen_addi_tl(temp, r2, con); + tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); + tcg_temp_free(temp); +} + /* Functions for arithmetic instructions */ #define OP_COND(insn)\ @@ -372,6 +392,9 @@ static void decode_ssr_opc(DisasContext *ctx, int op1) static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx) { int op1; + int r1, r2; + int32_t const16; + TCGv temp; op1 = MASK_OP_MAJOR(ctx->opcode); @@ -428,6 +451,37 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx) case OPC1_16_SSR_ST_W_POSTINC: decode_ssr_opc(ctx, op1); break; +/* SRRS-format */ + case OPC1_16_SRRS_ADDSC_A: + r2 = MASK_OP_SRRS_S2(ctx->opcode); + r1 = MASK_OP_SRRS_S1D(ctx->opcode); + const16 = MASK_OP_SRRS_N(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); + tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); + tcg_temp_free(temp); + break; +/* SLRO-format */ + case OPC1_16_SLRO_LD_A: + r1 = MASK_OP_SLRO_D(ctx->opcode); + const16 = MASK_OP_SLRO_OFF4(ctx->opcode); + gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); + break; + case OPC1_16_SLRO_LD_BU: + r1 = MASK_OP_SLRO_D(ctx->opcode); + const16 = MASK_OP_SLRO_OFF4(ctx->opcode); + gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); + break; + case OPC1_16_SLRO_LD_H: + r1 = MASK_OP_SLRO_D(ctx->opcode); + const16 = MASK_OP_SLRO_OFF4(ctx->opcode); + gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); + break; + case OPC1_16_SLRO_LD_W: + r1 = MASK_OP_SLRO_D(ctx->opcode); + const16 = MASK_OP_SLRO_OFF4(ctx->opcode); + gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); + break; } } -- 2.0.1