[Qemu-devel] [PATCH v2 08/15] target-tricore: Add instructions of SSR opcode format

[Bastian Koppelmann <kbastian@mail.uni-paderborn.de>]

Add instructions of SSR opcode format.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
v1 -> v2:
    - Remove AND in ST_B and ST_H instructions.
    - Load/Store instructions now use new TCGMemOp.
    - Move SSR instructions to one decode function.

 target-tricore/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 20ff6d7..4206a8a 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -330,6 +330,45 @@ static void decode_srr_opc(DisasContext *ctx, int op1)
     }
 }

+static void decode_ssr_opc(DisasContext *ctx, int op1)
+{
+    int r1, r2;
+
+    r1 = MASK_OP_SSR_S1(ctx->opcode);
+    r2 = MASK_OP_SSR_S2(ctx->opcode);
+
+    switch (op1) {
+    case OPC1_16_SSR_ST_A:
+        tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+        break;
+    case OPC1_16_SSR_ST_A_POSTINC:
+        tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+        break;
+    case OPC1_16_SSR_ST_B:
+        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+        break;
+    case OPC1_16_SSR_ST_B_POSTINC:
+        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+        break;
+    case OPC1_16_SSR_ST_H:
+        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
+        break;
+    case OPC1_16_SSR_ST_H_POSTINC:
+        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+        break;
+    case OPC1_16_SSR_ST_W:
+        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+        break;
+    case OPC1_16_SSR_ST_W_POSTINC:
+        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+        break;
+    }
+}
+
 static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
 {
     int op1;
@@ -378,6 +417,17 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
     case OPC1_16_SRR_XOR:
         decode_srr_opc(ctx, op1);
         break;
+/* SSR-format */
+    case OPC1_16_SSR_ST_A:
+    case OPC1_16_SSR_ST_A_POSTINC:
+    case OPC1_16_SSR_ST_B:
+    case OPC1_16_SSR_ST_B_POSTINC:
+    case OPC1_16_SSR_ST_H:
+    case OPC1_16_SSR_ST_H_POSTINC:
+    case OPC1_16_SSR_ST_W:
+    case OPC1_16_SSR_ST_W_POSTINC:
+        decode_ssr_opc(ctx, op1);
+        break;
     }
 }

--
2.0.1