From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Alex Bennée" <alex.bennee@linaro.org>,
rth@twiddle.net
Subject: [Qemu-devel] [PATCH 1/3] target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault
Date: Thu, 24 Jul 2014 16:52:53 +0100 [thread overview]
Message-ID: <1406217175-30267-2-git-send-email-alex.bennee@linaro.org> (raw)
In-Reply-To: <1406217175-30267-1-git-send-email-alex.bennee@linaro.org>
Otherwise we break quickly when we change TARGET_PAGE_SIZE.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a0e57cd..aa5d267 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4029,8 +4029,8 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
&page_size);
if (ret == 0) {
/* Map a single [sub]page. */
- phys_addr &= ~(hwaddr)0x3ff;
- address &= ~(target_ulong)0x3ff;
+ phys_addr &= TARGET_PAGE_MASK;
+ address &= TARGET_PAGE_MASK;
tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
return 0;
}
--
2.0.2
next prev parent reply other threads:[~2014-07-24 15:52 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-24 15:52 [Qemu-devel] [RFC PATCH 0/3] target-arm: Some fixes to page and TLB handling Alex Bennée
2014-07-24 15:52 ` Alex Bennée [this message]
2014-07-24 16:10 ` [Qemu-devel] [PATCH 1/3] target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault Peter Maydell
2014-07-24 15:52 ` [Qemu-devel] [PATCH 2/3] target-arm: A64: fix TLB flush instructions Alex Bennée
2014-07-24 16:09 ` Peter Maydell
2014-07-25 10:15 ` Alex Bennée
2014-07-24 15:52 ` [Qemu-devel] [PATCH 3/3] target-arm: A64: fix use 12 bit page tables for aarch64 Alex Bennée
2014-07-24 16:12 ` Peter Maydell
2014-07-24 16:15 ` [Qemu-devel] [RFC PATCH 0/3] target-arm: Some fixes to page and TLB handling Peter Maydell
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