From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39518) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XALJI-0000XT-K7 for qemu-devel@nongnu.org; Thu, 24 Jul 2014 11:52:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XALJD-0008PV-LL for qemu-devel@nongnu.org; Thu, 24 Jul 2014 11:52:00 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:60879 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XALJD-0008PQ-6K for qemu-devel@nongnu.org; Thu, 24 Jul 2014 11:51:55 -0400 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 24 Jul 2014 16:52:54 +0100 Message-Id: <1406217175-30267-3-git-send-email-alex.bennee@linaro.org> In-Reply-To: <1406217175-30267-1-git-send-email-alex.bennee@linaro.org> References: <1406217175-30267-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 2/3] target-arm: A64: fix TLB flush instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , rth@twiddle.net According to the ARM ARM we weren't correctly flushing the TLB entries where bits 63:56 didn't match bit 55 of the virtual address. This exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to 12 for aarch64. Signed-off-by: Alex Bennée diff --git a/target-arm/helper.c b/target-arm/helper.c index aa5d267..b0d0411 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1766,12 +1766,19 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, return CP_ACCESS_OK; } +/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions + * Page D4-1736 (DDI0487A.b) "For TLB maintenance instructions that + * take an address, the maintenance of VA[63:56] is interpreted as + * being the same as the maintenance of VA[55]" + */ + static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by VA (AArch64 version) */ ARMCPU *cpu = arm_env_get_cpu(env); - uint64_t pageaddr = value << 12; + uint64_t pageaddr = sextract64(value << 12, 0, 56); + tlb_flush_page(CPU(cpu), pageaddr); } @@ -1780,7 +1787,8 @@ static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, { /* Invalidate by VA, all ASIDs (AArch64 version) */ ARMCPU *cpu = arm_env_get_cpu(env); - uint64_t pageaddr = value << 12; + uint64_t pageaddr = sextract64(value << 12, 0, 56); + tlb_flush_page(CPU(cpu), pageaddr); } -- 2.0.2