From: Dongxue Zhang <elta.era@gmail.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Dongxue Zhang <elta.era@gmail.com>,
aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 2/2] target-mips/translate.c: Update OPC_SYNCI
Date: Tue, 29 Jul 2014 21:48:10 +0800 [thread overview]
Message-ID: <1406641690-6764-2-git-send-email-elta.era@gmail.com> (raw)
In-Reply-To: <1406641690-6764-1-git-send-email-elta.era@gmail.com>
Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved
in the same TB of the store instruction.
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
---
target-mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c381366..dc8afcf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15334,7 +15334,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS32R2);
- /* Treat as NOP. */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->bstate = BS_STOP;
break;
case OPC_BPOSGE32: /* MIPS DSP branch */
#if defined(TARGET_MIPS64)
--
1.8.1.2
next prev parent reply other threads:[~2014-07-29 13:49 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-29 13:48 [Qemu-devel] [PATCH 1/2] target-mips: Add synci instruction test Dongxue Zhang
2014-07-29 13:48 ` Dongxue Zhang [this message]
2014-09-10 15:12 ` [Qemu-devel] [PATCH 2/2] target-mips/translate.c: Update OPC_SYNCI Yongbok Kim
2014-09-10 15:13 ` [Qemu-devel] [PATCH 1/2] target-mips: Add synci instruction test Yongbok Kim
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