[Qemu-devel] [PATCH V2 2/2] target-mips/translate.c: Add judgement for msb and lsb

[Qemu-devel] [PATCH V2 2/2] target-mips/translate.c: Add judgement for msb and lsb

[Dongxue Zhang]

Compare the real msb and lsb, when lsb <= msb, tranlate the code. When
lsb > msb, just fall through and don't raise RI exception.

Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
---
 target-mips/translate.c | 43 ++++++++++++++++++++++++-------------------
 1 file changed, 24 insertions(+), 19 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index c381366..d40a4d3 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -3912,13 +3912,13 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
     gen_load_gpr(t1, rs);
     switch (opc) {
     case OPC_EXT:
-        if (lsb + msb > 31)
-            goto fail;
-        tcg_gen_shri_tl(t0, t1, lsb);
-        if (msb != 31) {
-            tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1);
-        } else {
-            tcg_gen_ext32s_tl(t0, t0);
+        if (lsb + msb <= 31) {
+            tcg_gen_shri_tl(t0, t1, lsb);
+            if (msb != 31) {
+                tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1);
+            } else {
+                tcg_gen_ext32s_tl(t0, t0);
+            }
         }
         break;
 #if defined(TARGET_MIPS64)
@@ -3938,28 +3938,33 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
         break;
 #endif
     case OPC_INS:
-        if (lsb > msb)
-            goto fail;
-        gen_load_gpr(t0, rt);
-        tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
-        tcg_gen_ext32s_tl(t0, t0);
+        if (lsb <= msb) {
+            gen_load_gpr(t0, rt);
+            tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
+            tcg_gen_ext32s_tl(t0, t0);
+        }
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DINSM:
-        gen_load_gpr(t0, rt);
-        tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1);
+        if (lsb <= (msb + 32)) {
+            gen_load_gpr(t0, rt);
+            tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1);
+        }
         break;
     case OPC_DINSU:
-        gen_load_gpr(t0, rt);
-        tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1);
+        if (lsb <= msb) {
+            gen_load_gpr(t0, rt);
+            tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1);
+        }
         break;
     case OPC_DINS:
-        gen_load_gpr(t0, rt);
-        tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
+        if (lsb <= msb) {
+            gen_load_gpr(t0, rt);
+            tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
+        }
         break;
 #endif
     default:
-fail:
         MIPS_INVAL("bitops");
         generate_exception(ctx, EXCP_RI);
         tcg_temp_free(t0);
-- 
1.8.1.2