From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45625) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XCURF-0006GC-6l for qemu-devel@nongnu.org; Wed, 30 Jul 2014 10:01:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XCUR5-0005AW-I9 for qemu-devel@nongnu.org; Wed, 30 Jul 2014 10:01:04 -0400 Received: from mail-pa0-x235.google.com ([2607:f8b0:400e:c03::235]:38919) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XCUR5-0005AH-BJ for qemu-devel@nongnu.org; Wed, 30 Jul 2014 10:00:55 -0400 Received: by mail-pa0-f53.google.com with SMTP id rd3so1568856pab.12 for ; Wed, 30 Jul 2014 07:00:54 -0700 (PDT) From: Dongxue Zhang Date: Wed, 30 Jul 2014 22:00:25 +0800 Message-Id: <1406728825-3123-1-git-send-email-elta.era@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PATCH V2 2/2] target-mips/translate.c: Add judgement for msb and lsb List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Dongxue Zhang , aurelien@aurel32.net Compare the real msb and lsb, when lsb <= msb, tranlate the code. When lsb > msb, just fall through and don't raise RI exception. Signed-off-by: Dongxue Zhang --- target-mips/translate.c | 43 ++++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index c381366..d40a4d3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -3912,13 +3912,13 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, gen_load_gpr(t1, rs); switch (opc) { case OPC_EXT: - if (lsb + msb > 31) - goto fail; - tcg_gen_shri_tl(t0, t1, lsb); - if (msb != 31) { - tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1); - } else { - tcg_gen_ext32s_tl(t0, t0); + if (lsb + msb <= 31) { + tcg_gen_shri_tl(t0, t1, lsb); + if (msb != 31) { + tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1); + } else { + tcg_gen_ext32s_tl(t0, t0); + } } break; #if defined(TARGET_MIPS64) @@ -3938,28 +3938,33 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, break; #endif case OPC_INS: - if (lsb > msb) - goto fail; - gen_load_gpr(t0, rt); - tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); - tcg_gen_ext32s_tl(t0, t0); + if (lsb <= msb) { + gen_load_gpr(t0, rt); + tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); + tcg_gen_ext32s_tl(t0, t0); + } break; #if defined(TARGET_MIPS64) case OPC_DINSM: - gen_load_gpr(t0, rt); - tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1); + if (lsb <= (msb + 32)) { + gen_load_gpr(t0, rt); + tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1); + } break; case OPC_DINSU: - gen_load_gpr(t0, rt); - tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1); + if (lsb <= msb) { + gen_load_gpr(t0, rt); + tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1); + } break; case OPC_DINS: - gen_load_gpr(t0, rt); - tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); + if (lsb <= msb) { + gen_load_gpr(t0, rt); + tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); + } break; #endif default: -fail: MIPS_INVAL("bitops"); generate_exception(ctx, EXCP_RI); tcg_temp_free(t0); -- 1.8.1.2