From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45246) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEIi9-00054W-QW for qemu-devel@nongnu.org; Mon, 04 Aug 2014 09:54:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XEIi7-0007L5-4U for qemu-devel@nongnu.org; Mon, 04 Aug 2014 09:54:01 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48908) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEIi6-0006mN-U2 for qemu-devel@nongnu.org; Mon, 04 Aug 2014 09:53:59 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XEIhd-0001BI-DK for qemu-devel@nongnu.org; Mon, 04 Aug 2014 14:53:29 +0100 From: Peter Maydell Date: Mon, 4 Aug 2014 14:53:28 +0100 Message-Id: <1407160408-4467-13-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1407160408-4467-1-git-send-email-peter.maydell@linaro.org> References: <1407160408-4467-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 12/12] target-arm: A64: fix TLB flush instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Alex Bennée According to the ARM ARM we weren't correctly flushing the TLB entries where bits 63:56 didn't match bit 55 of the virtual address. This exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to 12 for aarch64. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Message-id: 1406733627-24255-3-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target-arm/helper.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 35c11e7..f630d96 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1801,12 +1801,17 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, return CP_ACCESS_OK; } +/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions + * Page D4-1736 (DDI0487A.b) + */ + static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by VA (AArch64 version) */ ARMCPU *cpu = arm_env_get_cpu(env); - uint64_t pageaddr = value << 12; + uint64_t pageaddr = sextract64(value << 12, 0, 56); + tlb_flush_page(CPU(cpu), pageaddr); } @@ -1815,7 +1820,8 @@ static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, { /* Invalidate by VA, all ASIDs (AArch64 version) */ ARMCPU *cpu = arm_env_get_cpu(env); - uint64_t pageaddr = value << 12; + uint64_t pageaddr = sextract64(value << 12, 0, 56); + tlb_flush_page(CPU(cpu), pageaddr); } -- 1.9.1