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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 02/12] hw/arm/virt: formatting: memory map
Date: Mon,  4 Aug 2014 14:53:18 +0100	[thread overview]
Message-ID: <1407160408-4467-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1407160408-4467-1-git-send-email-peter.maydell@linaro.org>

From: Andrew Jones <drjones@redhat.com>

Add some spacing and zeros to make it easier to read and
modify the map. This patch has no functional changes. The
review looks ugly, but it's actually pretty easy to confirm
all the addresses are as they should be - thanks to the new
formatting ;-)

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 89532bd..ba94298 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -98,17 +98,17 @@ typedef struct VirtBoardInfo {
  */
 static const MemMapEntry a15memmap[] = {
     /* Space up to 0x8000000 is reserved for a boot ROM */
-    [VIRT_FLASH] = { 0, 0x8000000 },
-    [VIRT_CPUPERIPHS] = { 0x8000000, 0x20000 },
+    [VIRT_FLASH] =      {          0, 0x08000000 },
+    [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
     /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
-    [VIRT_GIC_DIST] = { 0x8000000, 0x10000 },
-    [VIRT_GIC_CPU] = { 0x8010000, 0x10000 },
-    [VIRT_UART] = { 0x9000000, 0x1000 },
-    [VIRT_RTC] = { 0x9010000, 0x1000 },
-    [VIRT_MMIO] = { 0xa000000, 0x200 },
+    [VIRT_GIC_DIST] =   { 0x08000000, 0x00010000 },
+    [VIRT_GIC_CPU] =    { 0x08010000, 0x00010000 },
+    [VIRT_UART] =       { 0x09000000, 0x00001000 },
+    [VIRT_RTC] =        { 0x09010000, 0x00001000 },
+    [VIRT_MMIO] =       { 0x0a000000, 0x00000200 },
     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
     /* 0x10000000 .. 0x40000000 reserved for PCI */
-    [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
+    [VIRT_MEM] =        { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
 };
 
 static const int a15irqmap[] = {
-- 
1.9.1

  parent reply	other threads:[~2014-08-04 13:54 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-04 13:53 [Qemu-devel] [PULL 00/12] target-arm queue Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 01/12] hw/arm/boot: Set PC correctly when loading AArch64 ELF files Peter Maydell
2014-08-04 13:53 ` Peter Maydell [this message]
2014-08-04 13:53 ` [Qemu-devel] [PULL 03/12] sd: sdhci: Fix ADMA dma_memory_read access Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 04/12] target-arm: A64: Break out aarch64_save/restore_sp Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 05/12] target-arm: A64: Respect SPSEL in ERET SP restore Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 06/12] target-arm: A64: Respect SPSEL when taking exceptions Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 07/12] target-arm: Make far_el1 an array Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 08/12] target-arm: Add ESR_EL2 and 3 Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 09/12] target-arm: Add FAR_EL2 " Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 10/12] target-arm: Fix bit test in sp_el0_access Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 11/12] target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault Peter Maydell
2014-08-04 13:53 ` [Qemu-devel] [PULL 12/12] target-arm: A64: fix TLB flush instructions Peter Maydell
2014-08-04 15:05 ` [Qemu-devel] [PULL 00/12] target-arm queue Peter Maydell

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