From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEIiA-00054X-2M for qemu-devel@nongnu.org; Mon, 04 Aug 2014 09:54:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XEIi8-0007Sa-8a for qemu-devel@nongnu.org; Mon, 04 Aug 2014 09:54:01 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48908) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEIi7-0006mN-Vl for qemu-devel@nongnu.org; Mon, 04 Aug 2014 09:54:00 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XEIhd-0001B2-87 for qemu-devel@nongnu.org; Mon, 04 Aug 2014 14:53:29 +0100 From: Peter Maydell Date: Mon, 4 Aug 2014 14:53:24 +0100 Message-Id: <1407160408-4467-9-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1407160408-4467-1-git-send-email-peter.maydell@linaro.org> References: <1407160408-4467-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 08/12] target-arm: Add ESR_EL2 and 3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias Reviewed-by: Alex Bennée Message-id: 1402994746-8328-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/cpu.h | 2 +- target-arm/helper.c | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index b755f99..3d9cf57 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -185,7 +185,7 @@ typedef struct CPUARMState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint32_t ifsr_el2; /* Fault status registers. */ - uint64_t esr_el[2]; + uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[2]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index b5f2e57..f4845b0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2127,6 +2127,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, + { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, @@ -2145,6 +2149,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, + { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, -- 1.9.1