From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34951) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEaU6-0004Hg-4h for qemu-devel@nongnu.org; Tue, 05 Aug 2014 04:52:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XEaU0-0004eU-3y for qemu-devel@nongnu.org; Tue, 05 Aug 2014 04:52:42 -0400 Received: from mail-qa0-x22f.google.com ([2607:f8b0:400d:c00::22f]:53654) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEaTz-0004eP-VX for qemu-devel@nongnu.org; Tue, 05 Aug 2014 04:52:36 -0400 Received: by mail-qa0-f47.google.com with SMTP id i13so610818qae.6 for ; Tue, 05 Aug 2014 01:52:34 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 5 Aug 2014 18:49:54 +1000 Message-Id: <1407228605-27081-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v4 00/10] target-arm: Parts of the AArch64 EL2/3 exception model List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Hi, This is a second round of AArch64 EL2/3 patches working on the exception model. Among other things adding HVC/SMC, interrupt routing to EL2/3 and Virtual IRQs/FIQs. The VIRQ/VFIQ support only adds the external signal delivery method. Patch 8 fails checkpatch, seems like a bug in checkpatch, CC:d Blue. This conflicts slightly with the PSCI emulation patches that Rob posted. A rebase should be trivial, hooking in the PSCI emulation calls in the HVC/SMC helpers. Note that part of this series has already been applied, I'm only posting the remaining patches. Cheers, Edgar v3 -> v4: * Coding style changes. * Add access spec for v8_el3_no_el2_cp_reginfo.HCR_EL2. * Move SCR to the el3 cpreg defs and add NO_MIGRATE to SCR_EL3. * Correct HCR.HCD and HCR.TSC RES0 behaviour. * Comment on hcr_write TLB flush. * Use uint32_t with explicit masking for imm16 in syndrome generator. * Add table lookup of interrupt masks in arm_cpu_set_irq. * Move M profile irq handling comment from cpu-exec.c to cpu.h. * Correct trap address for disabled HVC/SMD and for SMC routed to EL2. v2 -> v3: * Add more HCR bitfield macros * Flush TLB on hcr_write change of HCR RW, DC and PTW. * Fix hvc helper, HVC is undefined in secure mode. * Remove uint16_t imm16 syndrome gen change. * Replace c1_scr with scr_el3 v1 -> v2: * Avoid imm16 mask in syndrome generation * Use g_assert_not_reached() in arm_excp_unmasked() * Avoid some logic duplication in arm_excp_target_el and arm_excp_unmasked. * Put arm_excp_target_el in helper.c to start with. * Fix SMC disable (SMD or SCD) for ARMv7 only applies if EL2 exists * SCR_RES0_MASK -> SCR_MASK * HCR_RES0_MASK -> HCR_MASK * Fix SMC routing to EL2, only applies for NS EL1. * Fix CPreg defs for ESR_EL2/3 * Fix SMC helper, SMC routing to EL2 and SCR.SMD for AArch32. Edgar E. Iglesias (10): target-arm: Add HCR_EL2 target-arm: Add SCR_EL3 target-arm: A64: Refactor aarch64_cpu_do_interrupt target-arm: Break out exception masking to a separate func target-arm: Don't take interrupts targeting lower ELs target-arm: A64: Correct updates to FAR and ESR on exceptions target-arm: A64: Emulate the HVC insn target-arm: A64: Emulate the SMC insn target-arm: Add IRQ and FIQ routing to EL2 and 3 target-arm: Add support for VIRQ and VFIQ cpu-exec.c | 17 +++++- target-arm/cpu.c | 25 +++++---- target-arm/cpu.h | 127 ++++++++++++++++++++++++++++++++++++++++++- target-arm/helper-a64.c | 31 ++++++----- target-arm/helper.c | 133 ++++++++++++++++++++++++++++++++++++++++++++- target-arm/helper.h | 2 + target-arm/internals.h | 14 +++++ target-arm/op_helper.c | 66 ++++++++++++++++++++++ target-arm/translate-a64.c | 31 +++++++++-- 9 files changed, 410 insertions(+), 36 deletions(-) -- 1.9.1