From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43214) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEb7N-0002BZ-Sx for qemu-devel@nongnu.org; Tue, 05 Aug 2014 05:33:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XEb7A-0000uq-1Y for qemu-devel@nongnu.org; Tue, 05 Aug 2014 05:33:17 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:47990) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEb79-0000uK-SY for qemu-devel@nongnu.org; Tue, 05 Aug 2014 05:33:03 -0400 From: Fabian Aggeler Date: Tue, 5 Aug 2014 11:32:51 +0200 Message-ID: <1407231171-19572-3-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1407231171-19572-1-git-send-email-aggelerf@ethz.ch> References: <1407231171-19572-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 2/2] hw/arm/vexpress: add SP810 to the vexpress List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, alex.bennee@linaro.org The SP810, which is present in the Versatile Express motherboards, allows to set the timing reference to either REFCLK or TIMCLK. QEMU currently sets the SP804 timer to 1MHz by default. To reflect this, we set the TimerEn0Sel, TimerEn1Sel, TimerEn2Sel, and TimerEn3Sel of the system control register (SCCTRL) to TIMCLK (1). Signed-off-by: Fabian Aggeler --- hw/arm/vexpress.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index a88732c..0b6d31a 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -34,6 +34,7 @@ #include "hw/block/flash.h" #include "sysemu/device_tree.h" #include "qemu/error-report.h" +#include "hw/misc/arm_sp810.h" #include #define VEXPRESS_BOARD_ID 0x8e0 @@ -575,7 +576,10 @@ static void vexpress_common_init(VEDBoardInfo *daughterboard, qdev_init_nofail(sysctl); sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); - /* VE_SP810: not modelled */ + /* VE_SP810 (SP804 running at 1MHz (TIMCLK) by default) */ + sp810_init(map[VE_SP810], SCCTRL_TIMEREN0SEL | SCCTRL_TIMEREN1SEL + | SCCTRL_TIMEREN2SEL | SCCTRL_TIMEREN3SEL); + /* VE_SERIALPCI: not modelled */ pl041 = qdev_create(NULL, "pl041"); -- 1.8.3.2