From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XF7Dp-000407-Hm for qemu-devel@nongnu.org; Wed, 06 Aug 2014 15:50:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XF7Dg-0003iy-CU for qemu-devel@nongnu.org; Wed, 06 Aug 2014 15:50:05 -0400 Received: from mail-qg0-x22e.google.com ([2607:f8b0:400d:c04::22e]:40496) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XF7Dg-0003ij-8d for qemu-devel@nongnu.org; Wed, 06 Aug 2014 15:49:56 -0400 Received: by mail-qg0-f46.google.com with SMTP id z60so3264448qgd.5 for ; Wed, 06 Aug 2014 12:49:55 -0700 (PDT) Received: from pike.twiddle.home.com (ip-64-134-238-212.public.wayport.net. [64.134.238.212]) by mx.google.com with ESMTPSA id 70sm1995990qgx.24.2014.08.06.12.49.54 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Aug 2014 12:49:55 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 6 Aug 2014 09:49:37 -1000 Message-Id: <1407354580-11752-4-git-send-email-rth@twiddle.net> In-Reply-To: <1407354580-11752-1-git-send-email-rth@twiddle.net> References: <1407354580-11752-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 3/6] tcg-sparc: Fix setcond_i32 uninitialized value List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org We failed to swap c1 and c2 correctly for NE c2 == 0. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 08ca482..3b232d6 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -674,9 +674,12 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, case TCG_COND_NE: /* For equality, we can transform to inequality vs zero. */ if (c2 != 0) { - tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR); + tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); + c2 = TCG_REG_T1; + } else { + c2 = c1; } - c1 = TCG_REG_G0, c2 = ret, c2const = 0; + c1 = TCG_REG_G0, c2const = 0; cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); break; -- 1.9.3