From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52573) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XF7Dr-00041O-Ux for qemu-devel@nongnu.org; Wed, 06 Aug 2014 15:50:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XF7Dm-0003lt-0Z for qemu-devel@nongnu.org; Wed, 06 Aug 2014 15:50:07 -0400 Received: from mail-qg0-x234.google.com ([2607:f8b0:400d:c04::234]:58085) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XF7Dl-0003lG-TR for qemu-devel@nongnu.org; Wed, 06 Aug 2014 15:50:01 -0400 Received: by mail-qg0-f52.google.com with SMTP id f51so3328114qge.11 for ; Wed, 06 Aug 2014 12:50:01 -0700 (PDT) Received: from pike.twiddle.home.com (ip-64-134-238-212.public.wayport.net. [64.134.238.212]) by mx.google.com with ESMTPSA id 70sm1995990qgx.24.2014.08.06.12.49.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Aug 2014 12:50:00 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 6 Aug 2014 09:49:40 -1000 Message-Id: <1407354580-11752-7-git-send-email-rth@twiddle.net> In-Reply-To: <1407354580-11752-1-git-send-email-rth@twiddle.net> References: <1407354580-11752-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 6/6] tcg-sparc: Use UMULXHI instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Richard Henderson --- disas/sparc.c | 1 + tcg/sparc/tcg-target.c | 5 +++++ tcg/sparc/tcg-target.h | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/disas/sparc.c b/disas/sparc.c index 22ceac3..8e755d1 100644 --- a/disas/sparc.c +++ b/disas/sparc.c @@ -2034,6 +2034,7 @@ IMPDEP ("impdep2", 0x37), { "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, v9b }, { "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, v9b }, +{ "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, v9b }, }; diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 0a8c26a..0c4b028 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -210,6 +210,7 @@ static const int tcg_target_call_oarg_regs[] = { #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) #define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) +#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) @@ -1435,6 +1436,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], const_args[4], args[5], const_args[5], true); break; + case INDEX_op_muluh_i64: + tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); + break; gen_arith: tcg_out_arithc(s, a0, a1, a2, c2, c); @@ -1535,6 +1539,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_add2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } }, { INDEX_op_sub2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } }, + { INDEX_op_muluh_i64, { "R", "RZ", "RZ" } }, { INDEX_op_qemu_ld_i32, { "r", "A" } }, { INDEX_op_qemu_ld_i64, { "R", "A" } }, diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 099b308..0c4c8af 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -143,7 +143,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 0 #define TCG_TARGET_HAS_muls2_i64 0 -#define TCG_TARGET_HAS_muluh_i64 0 +#define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions #define TCG_TARGET_HAS_mulsh_i64 0 #define TCG_AREG0 TCG_REG_I0 -- 1.9.3