From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XF82R-0007GR-01 for qemu-devel@nongnu.org; Wed, 06 Aug 2014 16:42:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XF82I-0004o6-LL for qemu-devel@nongnu.org; Wed, 06 Aug 2014 16:42:22 -0400 Received: from e7.ny.us.ibm.com ([32.97.182.137]:33737) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XF82I-0004nk-Gp for qemu-devel@nongnu.org; Wed, 06 Aug 2014 16:42:14 -0400 Received: from /spool/local by e7.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 6 Aug 2014 16:42:14 -0400 From: Michael Roth Date: Wed, 6 Aug 2014 15:38:43 -0500 Message-Id: <1407357598-21541-34-git-send-email-mdroth@linux.vnet.ibm.com> In-Reply-To: <1407357598-21541-1-git-send-email-mdroth@linux.vnet.ibm.com> References: <1407357598-21541-1-git-send-email-mdroth@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 033/108] target-i386: fix set of registers zeroed on reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org From: Paolo Bonzini BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they should be (Intel Instruction Set Extensions Programming Reference 319433-015, pages 9-4 and 9-6). Same for YMM. XCR0 should be reset to 1. TSC and TSC_RESET were zeroed already by the memset, remove the explicit assignments. Cc: Andreas Faerber Reviewed-by: Michael S. Tsirkin Signed-off-by: Paolo Bonzini (cherry picked from commit 05e7e819d7d159a75a46354aead95e1199b8f168) Signed-off-by: Michael Roth --- target-i386/cpu.c | 3 +-- target-i386/cpu.h | 11 ++++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 8fd1497..553d0b8 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2476,8 +2476,7 @@ static void x86_cpu_reset(CPUState *s) cpu_breakpoint_remove_all(s, BP_CPU); cpu_watchpoint_remove_all(s, BP_CPU); - env->tsc_adjust = 0; - env->tsc = 0; + env->xcr0 = 1; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2a22a7d..e2244e9 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -797,6 +797,10 @@ typedef struct CPUX86State { target_ulong cr[5]; /* NOTE: cr1 is unused */ int32_t a20_mask; + BNDReg bnd_regs[4]; + BNDCSReg bndcs_regs; + uint64_t msr_bndcfgs; + /* FPU state */ unsigned int fpstt; /* top of stack index */ uint16_t fpus; @@ -819,6 +823,8 @@ typedef struct CPUX86State { XMMReg xmm_t0; MMXReg mmx_t0; + XMMReg ymmh_regs[CPU_NB_REGS]; + /* sysenter registers */ uint32_t sysenter_cs; target_ulong sysenter_esp; @@ -928,12 +934,7 @@ typedef struct CPUX86State { uint16_t fpus_vmstate; uint16_t fptag_vmstate; uint16_t fpregs_format_vmstate; - uint64_t xstate_bv; - XMMReg ymmh_regs[CPU_NB_REGS]; - BNDReg bnd_regs[4]; - BNDCSReg bndcs_regs; - uint64_t msr_bndcfgs; uint64_t xcr0; -- 1.9.1