From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55688) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XGvCG-0004wG-5b for qemu-devel@nongnu.org; Mon, 11 Aug 2014 15:24:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XGvC7-0002Tv-33 for qemu-devel@nongnu.org; Mon, 11 Aug 2014 15:23:56 -0400 From: Tom Musta Date: Mon, 11 Aug 2014 14:23:22 -0500 Message-Id: <1407785009-6538-2-git-send-email-tommusta@gmail.com> In-Reply-To: <1407785009-6538-1-git-send-email-tommusta@gmail.com> References: <1407785009-6538-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 1/8] target-ppc: Bug Fix: rlwinm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Tom Musta , agraf@suse.de The rlwinm specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Signed-off-by: Tom Musta --- target-ppc/translate.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b23933f..a27d063 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1672,11 +1672,9 @@ static void gen_rlwinm(DisasContext *ctx) } else { TCGv t0 = tcg_temp_new(); #if defined(TARGET_PPC64) - TCGv_i32 t1 = tcg_temp_new_i32(); - tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_rotli_i32(t1, t1, sh); - tcg_gen_extu_i32_i64(t0, t1); - tcg_temp_free_i32(t1); + tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)], 32, 32); + tcg_gen_rotli_i64(t0, t0, sh); #else tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); #endif -- 1.7.1