From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XGvCK-0004wL-Nt for qemu-devel@nongnu.org; Mon, 11 Aug 2014 15:24:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XGvCB-0002UJ-J7 for qemu-devel@nongnu.org; Mon, 11 Aug 2014 15:24:00 -0400 From: Tom Musta Date: Mon, 11 Aug 2014 14:23:23 -0500 Message-Id: <1407785009-6538-3-git-send-email-tommusta@gmail.com> In-Reply-To: <1407785009-6538-1-git-send-email-tommusta@gmail.com> References: <1407785009-6538-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 2/8] target-ppc: Bug Fix: rlwnm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Tom Musta , agraf@suse.de The rlwnm specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Signed-off-by: Tom Musta --- target-ppc/translate.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a27d063..48f13a9 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1695,7 +1695,7 @@ static void gen_rlwnm(DisasContext *ctx) uint32_t mb, me; TCGv t0; #if defined(TARGET_PPC64) - TCGv_i32 t1, t2; + TCGv t1; #endif mb = MB(ctx->opcode); @@ -1703,14 +1703,11 @@ static void gen_rlwnm(DisasContext *ctx) t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); #if defined(TARGET_PPC64) - t1 = tcg_temp_new_i32(); - t2 = tcg_temp_new_i32(); - tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_trunc_i64_i32(t2, t0); - tcg_gen_rotl_i32(t1, t1, t2); - tcg_gen_extu_i32_i64(t0, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); + t1 = tcg_temp_new_i64(); + tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)], 32, 32); + tcg_gen_rotl_i64(t0, t1, t0); + tcg_temp_free_i64(t1); #else tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); #endif @@ -1721,6 +1718,9 @@ static void gen_rlwnm(DisasContext *ctx) #endif tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); } else { +#if defined(TARGET_PPC64) + tcg_gen_andi_tl(t0, t0, MASK(32, 63)); +#endif tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); } tcg_temp_free(t0); -- 1.7.1