From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, agraf@suse.de
Subject: [Qemu-devel] [PATCH 4/8] target-ppc: Bug Fix: mullw
Date: Mon, 11 Aug 2014 14:23:25 -0500 [thread overview]
Message-ID: <1407785009-6538-5-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1407785009-6538-1-git-send-email-tommusta@gmail.com>
For 64-bit implementations, the mullw result is the 64 bit product
of the sign-extended least significant 32 bits of the source
registers.
Fix the code to properly sign extend the source operands and produce
a 64 bit product.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f4cc495..41a5aea 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1125,9 +1125,20 @@ static void gen_mulhwu(DisasContext *ctx)
/* mullw mullw. */
static void gen_mullw(DisasContext *ctx)
{
+#if defined(TARGET_PPC64)
+ TCGv_i64 t0, t1;
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+#else
tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rB(ctx->opcode)]);
tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
+#endif
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
}
--
1.7.1
next prev parent reply other threads:[~2014-08-11 19:24 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-11 19:23 [Qemu-devel] [PATCH 0/8] target-ppc: Bug Fixes for 64 Bit FXU Instructions Tom Musta
2014-08-11 19:23 ` [Qemu-devel] [PATCH 1/8] target-ppc: Bug Fix: rlwinm Tom Musta
2014-08-15 18:34 ` Richard Henderson
2014-08-15 19:52 ` Richard Henderson
2014-08-11 19:23 ` [Qemu-devel] [PATCH 2/8] target-ppc: Bug Fix: rlwnm Tom Musta
2014-08-15 19:54 ` Richard Henderson
2014-08-11 19:23 ` [Qemu-devel] [PATCH 3/8] target-ppc: Bug Fix: rlwimi Tom Musta
2014-08-15 20:05 ` Richard Henderson
2014-08-18 19:51 ` Tom Musta
2014-08-11 19:23 ` Tom Musta [this message]
2014-08-15 20:07 ` [Qemu-devel] [PATCH 4/8] target-ppc: Bug Fix: mullw Richard Henderson
2014-08-11 19:23 ` [Qemu-devel] [PATCH 5/8] target-ppc: Bug Fix: mullwo Tom Musta
2014-08-15 20:11 ` Richard Henderson
2014-08-11 19:23 ` [Qemu-devel] [PATCH 6/8] target-ppc: Bug Fix: mulldo OV Detection Tom Musta
2014-08-15 20:16 ` Richard Henderson
2014-08-11 19:23 ` [Qemu-devel] [PATCH 7/8] target-ppc: Bug Fix: srawi Tom Musta
2014-08-11 19:23 ` [Qemu-devel] [PATCH 8/8] target-ppc: Bug Fix: srad Tom Musta
2014-08-15 20:17 ` Richard Henderson
2014-08-12 3:06 ` [Qemu-devel] [PATCH 0/8] target-ppc: Bug Fixes for 64 Bit FXU Instructions David Gibson
2014-08-12 11:40 ` Tom Musta
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