From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XGvCX-0005GG-PU for qemu-devel@nongnu.org; Mon, 11 Aug 2014 15:24:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XGvCO-0002WX-Fe for qemu-devel@nongnu.org; Mon, 11 Aug 2014 15:24:13 -0400 From: Tom Musta Date: Mon, 11 Aug 2014 14:23:26 -0500 Message-Id: <1407785009-6538-6-git-send-email-tommusta@gmail.com> In-Reply-To: <1407785009-6538-1-git-send-email-tommusta@gmail.com> References: <1407785009-6538-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 5/8] target-ppc: Bug Fix: mullwo List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Tom Musta , agraf@suse.de On 64-bit implementations, the mullwo result is the 64 bit product of the signed 32 bit operands. Fix the implementation to properly deposit the upper 32 bits into the target register. Signed-off-by: Tom Musta --- target-ppc/translate.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 41a5aea..4904665 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1148,11 +1148,20 @@ static void gen_mullwo(DisasContext *ctx) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); +#if defined(TARGET_PPC64) + TCGv_i64 t2 = tcg_temp_new_i64(); +#endif tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); tcg_gen_muls2_i32(t0, t1, t0, t1); tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); +#if defined(TARGET_PPC64) + tcg_gen_ext_i32_tl(t2, t1); + tcg_gen_deposit_i64(cpu_gpr[rD(ctx->opcode)], + cpu_gpr[rD(ctx->opcode)], t2, 32, 32); + tcg_temp_free(t2); +#endif tcg_gen_sari_i32(t0, t0, 31); tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); -- 1.7.1