From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42390) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHCOh-0004v8-8c for qemu-devel@nongnu.org; Tue, 12 Aug 2014 09:46:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XHCOY-0002K9-8H for qemu-devel@nongnu.org; Tue, 12 Aug 2014 09:45:55 -0400 From: Tom Musta Date: Tue, 12 Aug 2014 08:45:05 -0500 Message-Id: <1407851110-8075-4-git-send-email-tommusta@gmail.com> In-Reply-To: <1407851110-8075-1-git-send-email-tommusta@gmail.com> References: <1407851110-8075-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [V2 PATCH 3/8] target-ppc: Bug Fix: rlwimi List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Tom Musta , agraf@suse.de, david@gibson.dropbear.id.au The rlwimi specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Also fix the special case of MB=31 and ME=0 to copy the entire contents of the source GPR. Examples: R3 FFFFFFFFFFFFFFF0 rlwimi 3,3,29,14,1 R3 expected : 1FFFFFFE3FFFFFFE R3 actual : 000000003FFFFFFE (without this patch) R3 ED7EB4DD824F0853 rlwimi 3,3,10,31,0 R3 expected : 3C214E09024F0853 R3 actual : 00000000024F0853 (without this patch) Signed-off-by: Tom Musta --- target-ppc/translate.c | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 48f13a9..f4cc495 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1614,17 +1614,19 @@ static void gen_rlwimi(DisasContext *ctx) me = ME(ctx->opcode); sh = SH(ctx->opcode); if (likely(sh == 0 && mb == 0 && me == 31)) { +#if defined(TARGET_PPC64) + tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); +#else tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); +#endif } else { target_ulong mask; TCGv t1; TCGv t0 = tcg_temp_new(); #if defined(TARGET_PPC64) - TCGv_i32 t2 = tcg_temp_new_i32(); - tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_rotli_i32(t2, t2, sh); - tcg_gen_extu_i32_i64(t0, t2); - tcg_temp_free_i32(t2); + tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)], 32, 32); + tcg_gen_rotli_i64(t0, t0, sh); #else tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); #endif -- 1.7.1