From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42419) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHCOm-0004yZ-Ff for qemu-devel@nongnu.org; Tue, 12 Aug 2014 09:46:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XHCOd-0002Sv-8W for qemu-devel@nongnu.org; Tue, 12 Aug 2014 09:46:00 -0400 From: Tom Musta Date: Tue, 12 Aug 2014 08:45:06 -0500 Message-Id: <1407851110-8075-5-git-send-email-tommusta@gmail.com> In-Reply-To: <1407851110-8075-1-git-send-email-tommusta@gmail.com> References: <1407851110-8075-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [V2 PATCH 4/8] target-ppc: Bug Fix: mullw List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Tom Musta , agraf@suse.de, david@gibson.dropbear.id.au For 64-bit implementations, the mullw result is the 64 bit product of the sign-extended least significant 32 bits of the source registers. Fix the code to properly sign extend the source operands and produce a 64 bit product. Example: R3 00000000002F37A0 R4 41C33D242F816715 mullw 3,3,4 R3 expected : 0008C3146AE0F020 R3 actual : 000000006AE0F020 (without this patch) Signed-off-by: Tom Musta --- target-ppc/translate.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f4cc495..41a5aea 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1125,9 +1125,20 @@ static void gen_mulhwu(DisasContext *ctx) /* mullw mullw. */ static void gen_mullw(DisasContext *ctx) { +#if defined(TARGET_PPC64) + TCGv_i64 t0, t1; + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); + tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); +#else tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); +#endif if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); } -- 1.7.1