From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHWLQ-0006B2-Jx for qemu-devel@nongnu.org; Wed, 13 Aug 2014 07:03:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XHWLK-0002Ss-Jd for qemu-devel@nongnu.org; Wed, 13 Aug 2014 07:03:52 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:54500) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHWLK-0002Sf-CX for qemu-devel@nongnu.org; Wed, 13 Aug 2014 07:03:46 -0400 From: Bastian Koppelmann Date: Wed, 13 Aug 2014 13:07:20 +0100 Message-Id: <1407931644-25602-12-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1407931644-25602-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1407931644-25602-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v5 11/15] target-tricore: Add instructions of SBC and SBRN opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Add instructions of SBC and SBRN opcode format. Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target-tricore/translate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index b06f856..87b5ad3 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -389,6 +389,8 @@ static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, int r2 , int32_t constant , int32_t offset) { + TCGv temp; + switch (opc) { /* SB-format jumps */ case OPC1_16_SB_J: @@ -405,6 +407,26 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, case OPC1_16_SB_JNZ: gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); break; +/* SBC-format jumps */ + case OPC1_16_SBC_JEQ: + gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); + break; + case OPC1_16_SBC_JNE: + gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); + break; +/* SBRN-format jumps */ + case OPC1_16_SBRN_JZ_T: + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); + gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); + tcg_temp_free(temp); + break; + case OPC1_16_SBRN_JNZ_T: + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); + gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); + tcg_temp_free(temp); + break; default: printf("Branch Error at %x\n", ctx->pc); } @@ -714,6 +736,20 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx) address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); gen_compute_branch(ctx, op1, 0, 0, 0, address); break; +/* SBC-format */ + case OPC1_16_SBC_JEQ: + case OPC1_16_SBC_JNE: + address = MASK_OP_SBC_DISP4(ctx->opcode); + const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + break; +/* SBRN-format */ + case OPC1_16_SBRN_JNZ_T: + case OPC1_16_SBRN_JZ_T: + address = MASK_OP_SBRN_DISP4(ctx->opcode); + const16 = MASK_OP_SBRN_N(ctx->opcode); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + break; } } -- 2.0.4