From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56722) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHxa6-0004gT-04 for qemu-devel@nongnu.org; Thu, 14 Aug 2014 12:08:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XHxa1-0001sz-2M for qemu-devel@nongnu.org; Thu, 14 Aug 2014 12:08:49 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60532) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHxa0-0001ss-PO for qemu-devel@nongnu.org; Thu, 14 Aug 2014 12:08:44 -0400 Date: Thu, 14 Aug 2014 18:09:12 +0200 From: "Michael S. Tsirkin" Message-ID: <1408032488-11096-11-git-send-email-mst@redhat.com> References: <1408032488-11096-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1408032488-11096-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL 10/12] e1000: correctly handle phy_ctrl reserved & self-clearing bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Anthony Liguori , Gabriel Somlo , "Gabriel L. Somlo" , Stefan Hajnoczi , Amos Kong From: "Gabriel L. Somlo" Make phyreg_writeops responsible for actually writing their respective phy registers, rather than rely on set_mdic() to do it on their behalf. The only current instance of phyreg_writeops is set_phy_ctrl(); modify it to write the register on its own, while also correctly handling reserved and self-clearing bits. have_autoneg() does not need to check for MII_CR_RESTART_AUTO_NEG, since the only time the flag comes into play is during set_phy_ctrl(), and, following this patch, never actually gets written to the phy control register. Signed-off-by: Gabriel Somlo Reviewed-by: Michael S. Tsirkin Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/net/e1000.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 0fc29a0..04c0f91 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -186,21 +186,31 @@ e1000_link_up(E1000State *s) s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS; } +static bool +have_autoneg(E1000State *s) +{ + return (s->compat_flags & E1000_FLAG_AUTONEG) && + (s->phy_reg[PHY_CTRL] & MII_CR_AUTO_NEG_EN); +} + static void set_phy_ctrl(E1000State *s, int index, uint16_t val) { + /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */ + s->phy_reg[PHY_CTRL] = val & ~(0x3f | + MII_CR_RESET | + MII_CR_RESTART_AUTO_NEG); + /* * QEMU 1.3 does not support link auto-negotiation emulation, so if we * migrate during auto negotiation, after migration the link will be * down. */ - if (!(s->compat_flags & E1000_FLAG_AUTONEG)) { - return; - } - if ((val & MII_CR_AUTO_NEG_EN) && (val & MII_CR_RESTART_AUTO_NEG)) { + if (have_autoneg(s) && (val & MII_CR_RESTART_AUTO_NEG)) { e1000_link_down(s); DBGOUT(PHY, "Start link auto negotiation\n"); - timer_mod(s->autoneg_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); + timer_mod(s->autoneg_timer, + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); } } @@ -446,8 +456,9 @@ set_mdic(E1000State *s, int index, uint32_t val) } else { if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) { phyreg_writeops[addr](s, index, data); + } else { + s->phy_reg[addr] = data; } - s->phy_reg[addr] = data; } } s->mac_reg[MDIC] = val | E1000_MDIC_READY; @@ -848,14 +859,6 @@ receive_filter(E1000State *s, const uint8_t *buf, int size) return 0; } -static bool -have_autoneg(E1000State *s) -{ - return (s->compat_flags & E1000_FLAG_AUTONEG) && - (s->phy_reg[PHY_CTRL] & MII_CR_AUTO_NEG_EN) && - (s->phy_reg[PHY_CTRL] & MII_CR_RESTART_AUTO_NEG); -} - static void e1000_set_link_status(NetClientState *nc) { -- MST