[Qemu-devel] [PATCH v3 0/2] Add SP810 to Versatile Express boards

[Qemu-devel] [PATCH v3 0/2] Add SP810 to Versatile Express boards

[Fabian Aggeler]

Hi,

The Versatile Express emulation in QEMU currently does not
have a model of the SP810 used in real hardware. The registers
provided by this System Controller can be used to set the
frequency of the SP804 timers. On newer releases of the board
the SP804 is set to 32kHz by default and has to be increased
by writing to the SCCTRL. See: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2011-January/038696.html

Since QEMU sets the SP804 timers to 1MHz by default this should
be reflected in the SCCTRL register. These two patches add a
model of the SP804 to the vexpress-boards and sets the SCCTRL 
register so that software that queries this register behaves 
as expected.

Feedback is greatly appreciated!

Best,
Fabian

v2 -> v3:
* removed duplicate comment
* split SCCTRL property into 4 individual properties
* moved initialisation back to vexpress.c

v2: https://lists.nongnu.org/archive/html/qemu-devel/2014-08/msg00629.html

v1 -> v2:
* TIMERENXSEL prefixed with register name
* removed casts
* created header file 

v1: https://lists.nongnu.org/archive/html/qemu-devel/2014-07/msg02572.html

Fabian Aggeler (2):
  hw/misc/arm_sp810: Create SP810 device
  hw/arm/vexpress: add SP810 to the vexpress

 default-configs/arm-softmmu.mak |   1 +
 hw/arm/vexpress.c               |  13 ++++-
 hw/misc/Makefile.objs           |   1 +
 hw/misc/arm_sp810.c             | 109 ++++++++++++++++++++++++++++++++++++++++
 include/hw/misc/arm_sp810.h     |  80 +++++++++++++++++++++++++++++
 5 files changed, 202 insertions(+), 2 deletions(-)
 create mode 100644 hw/misc/arm_sp810.c
 create mode 100644 include/hw/misc/arm_sp810.h

-- 
1.8.3.2

[Qemu-devel] [PATCH v3 1/2] hw/misc/arm_sp810: Create SP810 device

[Fabian Aggeler]

This adds a device model for the PrimeXsys System Controller (SP810)
which is present in the Versatile Express motherboards. It is
so far read-only but allows to read the SCCTRL register.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
---
 default-configs/arm-softmmu.mak |   1 +
 hw/misc/Makefile.objs           |   1 +
 hw/misc/arm_sp810.c             | 109 ++++++++++++++++++++++++++++++++++++++++
 include/hw/misc/arm_sp810.h     |  80 +++++++++++++++++++++++++++++
 4 files changed, 191 insertions(+)
 create mode 100644 hw/misc/arm_sp810.c
 create mode 100644 include/hw/misc/arm_sp810.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index f3513fa..67ba99a 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -55,6 +55,7 @@ CONFIG_PL181=y
 CONFIG_PL190=y
 CONFIG_PL310=y
 CONFIG_PL330=y
+CONFIG_SP810=y
 CONFIG_CADENCE=y
 CONFIG_XGMAC=y
 CONFIG_EXYNOS4=y
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 979e532..49d023b 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -13,6 +13,7 @@ common-obj-$(CONFIG_PL310) += arm_l2x0.o
 common-obj-$(CONFIG_INTEGRATOR_DEBUG) += arm_integrator_debug.o
 common-obj-$(CONFIG_A9SCU) += a9scu.o
 common-obj-$(CONFIG_ARM11SCU) += arm11scu.o
+common-obj-$(CONFIG_SP810) += arm_sp810.o
 
 # PKUnity SoC devices
 common-obj-$(CONFIG_PUV3) += puv3_pm.o
diff --git a/hw/misc/arm_sp810.c b/hw/misc/arm_sp810.c
new file mode 100644
index 0000000..7aff9bd
--- /dev/null
+++ b/hw/misc/arm_sp810.c
@@ -0,0 +1,109 @@
+/*
+ * ARM PrimeXsys System Controller (SP810)
+ *
+ * Copyright (C) 2014 Fabian Aggeler <aggelerf@ethz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "hw/misc/arm_sp810.h"
+
+static const VMStateDescription vmstate_arm_sysctl = {
+    .name = "arm_sp810",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8(timeren0_sel, arm_sp810_state),
+        VMSTATE_UINT8(timeren1_sel, arm_sp810_state),
+        VMSTATE_UINT8(timeren2_sel, arm_sp810_state),
+        VMSTATE_UINT8(timeren3_sel, arm_sp810_state),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static uint64_t arm_sp810_read(void *opaque, hwaddr offset, unsigned size)
+{
+    arm_sp810_state *s = opaque;
+
+    switch (offset) {
+    case SCCTRL:
+        return (s->timeren3_sel << 21) | (s->timeren2_sel << 19)
+                | (s->timeren1_sel << 17) | (s->timeren0_sel << 15);
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                "arm_sp810_read: Register not yet implemented: %s\n",
+                HWADDR_PRIx);
+        return 0;
+    }
+}
+
+static void arm_sp810_write(void *opaque, hwaddr offset,
+                            uint64_t val, unsigned size)
+{
+    switch (offset) {
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                "arm_sp810_write: Register not yet implemented: %s\n",
+                HWADDR_PRIx);
+        return;
+    }
+}
+
+static const MemoryRegionOps arm_sp810_ops = {
+    .read = arm_sp810_read,
+    .write = arm_sp810_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void arm_sp810_init(Object *obj)
+{
+    arm_sp810_state *s = ARM_SP810(obj);
+
+    memory_region_init_io(&s->iomem, obj, &arm_sp810_ops, s, "arm-sp810",
+                          0x1000);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+}
+
+static Property arm_sp810_properties[] = {
+    DEFINE_PROP_UINT8("timeren0-sel", arm_sp810_state, timeren0_sel,
+                                                       SCCTRL_TIMER_REFCLK),
+    DEFINE_PROP_UINT8("timeren1-sel", arm_sp810_state, timeren1_sel,
+                                                       SCCTRL_TIMER_REFCLK),
+    DEFINE_PROP_UINT8("timeren2-sel", arm_sp810_state, timeren2_sel,
+                                                       SCCTRL_TIMER_REFCLK),
+    DEFINE_PROP_UINT8("timeren3-sel", arm_sp810_state, timeren3_sel,
+                                                       SCCTRL_TIMER_REFCLK),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void arm_sp810_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->vmsd = &vmstate_arm_sysctl;
+    dc->props = arm_sp810_properties;
+}
+
+static const TypeInfo arm_sp810_info = {
+    .name          = TYPE_ARM_SP810,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(arm_sp810_state),
+    .instance_init = arm_sp810_init,
+    .class_init    = arm_sp810_class_init,
+};
+
+static void arm_sp810_register_types(void)
+{
+    type_register_static(&arm_sp810_info);
+}
+
+type_init(arm_sp810_register_types)
diff --git a/include/hw/misc/arm_sp810.h b/include/hw/misc/arm_sp810.h
new file mode 100644
index 0000000..78c11f4
--- /dev/null
+++ b/include/hw/misc/arm_sp810.h
@@ -0,0 +1,80 @@
+/*
+ * ARM PrimeXsys System Controller (SP810)
+ *
+ * Copyright (C) 2014 Fabian Aggeler <aggelerf@ethz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef HW_MISC_ARM_SP810H
+#define HW_MISC_ARM_SP810H
+
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+
+#define TYPE_ARM_SP810 "arm_sp810"
+#define ARM_SP810(obj) OBJECT_CHECK(arm_sp810_state, (obj), TYPE_ARM_SP810)
+
+/* Register Offsets */
+#define SCCTRL      0x000
+#define SCSYSSTAT   0x004
+#define SCIMCTRL    0x008
+#define SCIMSTAT    0x00C
+#define SCXTALCTRL  0x010
+#define SCPLLCTRL   0x014
+#define SCPLLFCTRL  0x018
+#define SCPERCTRL0  0x01C
+#define SCPERCTRL1  0x020
+#define SCPEREN     0x024
+#define SCPERDIS    0x028
+#define SCPERCLKEN  0x02C
+#define SCPERSTAT   0x030
+#define SCSYSID0    0xEE0
+#define SCSYSID1    0xEE4
+#define SCSYSID2    0xEE8
+#define SCSYSID3    0xEEC
+#define SCITCR      0xF00
+#define SCITIR0     0xF04
+#define SCITIR1     0xF08
+#define SCITOR      0xF0C
+#define SCCNTCTRL   0xF10
+#define SCCNTDATA   0xF14
+#define SCCNTSTEP   0xF18
+#define SCPERIPHID0 0xFE0
+#define SCPERIPHID1 0xFE4
+#define SCPERIPHID2 0xFE8
+#define SCPERIPHID3 0xFEC
+#define SCPCELLID0  0xFF0
+#define SCPCELLID1  0xFF4
+#define SCPCELLID2  0xFF8
+#define SCPCELLID3  0xFFC
+
+/* System Control Register bits */
+#define SCCTRL_TIMEREN0SEL (1 << 15)
+#define SCCTRL_TIMEREN1SEL (1 << 17)
+#define SCCTRL_TIMEREN2SEL (1 << 19)
+#define SCCTRL_TIMEREN3SEL (1 << 21)
+
+#define SCCTRL_TIMER_REFCLK 0
+#define SCCTRL_TIMER_TIMCLK 1
+
+typedef struct {
+    SysBusDevice parent_obj;
+    MemoryRegion iomem;
+
+    uint8_t timeren0_sel;
+    uint8_t timeren1_sel;
+    uint8_t timeren2_sel;
+    uint8_t timeren3_sel;
+} arm_sp810_state;
+
+#endif
-- 
1.8.3.2

[Qemu-devel] [PATCH v3 2/2] hw/arm/vexpress: add SP810 to the vexpress

[Fabian Aggeler]

The SP810, which is present in the Versatile Express motherboards,
allows to set the timing reference to either REFCLK or TIMCLK.
QEMU currently sets the SP804 timer to 1MHz by default. To reflect
this, we set the TimerEn0Sel, TimerEn1Sel, TimerEn2Sel, and
TimerEn3Sel of the system control register (SCCTRL) to TIMCLK (1).

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
---
 hw/arm/vexpress.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index a88732c..086f68a 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -34,6 +34,7 @@
 #include "hw/block/flash.h"
 #include "sysemu/device_tree.h"
 #include "qemu/error-report.h"
+#include "hw/misc/arm_sp810.h"
 #include <libfdt.h>
 
 #define VEXPRESS_BOARD_ID 0x8e0
@@ -512,7 +513,7 @@ static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name,
 static void vexpress_common_init(VEDBoardInfo *daughterboard,
                                  MachineState *machine)
 {
-    DeviceState *dev, *sysctl, *pl041;
+    DeviceState *dev, *sysctl, *pl041, *sp810;
     qemu_irq pic[64];
     uint32_t sys_id;
     DriveInfo *dinfo;
@@ -575,7 +576,15 @@ static void vexpress_common_init(VEDBoardInfo *daughterboard,
     qdev_init_nofail(sysctl);
     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 
-    /* VE_SP810: not modelled */
+    /* VE_SP810 (SP804 running at 1MHz (TIMCLK) by default) */
+    sp810 = qdev_create(NULL, TYPE_ARM_SP810);
+    qdev_prop_set_uint8(sp810, "timeren0-sel", SCCTRL_TIMER_TIMCLK);
+    qdev_prop_set_uint8(sp810, "timeren1-sel", SCCTRL_TIMER_TIMCLK);
+    qdev_prop_set_uint8(sp810, "timeren2-sel", SCCTRL_TIMER_TIMCLK);
+    qdev_prop_set_uint8(sp810, "timeren3-sel", SCCTRL_TIMER_TIMCLK);
+    qdev_init_nofail(sp810);
+    sysbus_mmio_map(SYS_BUS_DEVICE(sp810), 0, map[VE_SP810]);
+
     /* VE_SERIALPCI: not modelled */
 
     pl041 = qdev_create(NULL, "pl041");
-- 
1.8.3.2

Re: [Qemu-devel] [PATCH v3 1/2] hw/misc/arm_sp810: Create SP810 device

[Peter Maydell]

On 17 August 2014 15:24, Fabian Aggeler <aggelerf@ethz.ch> wrote:
> This adds a device model for the PrimeXsys System Controller (SP810)
> which is present in the Versatile Express motherboards. It is
> so far read-only but allows to read the SCCTRL register.
>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> ---
>  default-configs/arm-softmmu.mak |   1 +
>  hw/misc/Makefile.objs           |   1 +
>  hw/misc/arm_sp810.c             | 109 ++++++++++++++++++++++++++++++++++++++++
>  include/hw/misc/arm_sp810.h     |  80 +++++++++++++++++++++++++++++
>  4 files changed, 191 insertions(+)
>  create mode 100644 hw/misc/arm_sp810.c
>  create mode 100644 include/hw/misc/arm_sp810.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index f3513fa..67ba99a 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -55,6 +55,7 @@ CONFIG_PL181=y
>  CONFIG_PL190=y
>  CONFIG_PL310=y
>  CONFIG_PL330=y
> +CONFIG_SP810=y
>  CONFIG_CADENCE=y
>  CONFIG_XGMAC=y
>  CONFIG_EXYNOS4=y
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index 979e532..49d023b 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -13,6 +13,7 @@ common-obj-$(CONFIG_PL310) += arm_l2x0.o
>  common-obj-$(CONFIG_INTEGRATOR_DEBUG) += arm_integrator_debug.o
>  common-obj-$(CONFIG_A9SCU) += a9scu.o
>  common-obj-$(CONFIG_ARM11SCU) += arm11scu.o
> +common-obj-$(CONFIG_SP810) += arm_sp810.o

We mostly don't use the 'arm' prefix (compare pl330, pl011,
and other examples for other architectures), so you can
remove it from filenames and variable names here.

>
>  # PKUnity SoC devices
>  common-obj-$(CONFIG_PUV3) += puv3_pm.o
> diff --git a/hw/misc/arm_sp810.c b/hw/misc/arm_sp810.c
> new file mode 100644
> index 0000000..7aff9bd
> --- /dev/null
> +++ b/hw/misc/arm_sp810.c
> @@ -0,0 +1,109 @@
> +/*
> + * ARM PrimeXsys System Controller (SP810)
> + *
> + * Copyright (C) 2014 Fabian Aggeler <aggelerf@ethz.ch>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include "hw/misc/arm_sp810.h"
> +
> +static const VMStateDescription vmstate_arm_sysctl = {

^^^ should be vmstate_sp810.

> +    .name = "arm_sp810",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINT8(timeren0_sel, arm_sp810_state),
> +        VMSTATE_UINT8(timeren1_sel, arm_sp810_state),
> +        VMSTATE_UINT8(timeren2_sel, arm_sp810_state),
> +        VMSTATE_UINT8(timeren3_sel, arm_sp810_state),

These are read only properties, so you don't need to save them.

> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> +
> +static uint64_t arm_sp810_read(void *opaque, hwaddr offset, unsigned size)
> +{
> +    arm_sp810_state *s = opaque;
> +
> +    switch (offset) {
> +    case SCCTRL:
> +        return (s->timeren3_sel << 21) | (s->timeren2_sel << 19)
> +                | (s->timeren1_sel << 17) | (s->timeren0_sel << 15);
> +    default:
> +        qemu_log_mask(LOG_UNIMP,
> +                "arm_sp810_read: Register not yet implemented: %s\n",
> +                HWADDR_PRIx);
> +        return 0;
> +    }
> +}
> +
> +static void arm_sp810_write(void *opaque, hwaddr offset,
> +                            uint64_t val, unsigned size)
> +{
> +    switch (offset) {
> +    default:
> +        qemu_log_mask(LOG_UNIMP,
> +                "arm_sp810_write: Register not yet implemented: %s\n",
> +                HWADDR_PRIx);
> +        return;
> +    }
> +}
> +
> +static const MemoryRegionOps arm_sp810_ops = {
> +    .read = arm_sp810_read,
> +    .write = arm_sp810_write,
> +    .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void arm_sp810_init(Object *obj)
> +{
> +    arm_sp810_state *s = ARM_SP810(obj);
> +
> +    memory_region_init_io(&s->iomem, obj, &arm_sp810_ops, s, "arm-sp810",
> +                          0x1000);
> +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
> +}
> +
> +static Property arm_sp810_properties[] = {
> +    DEFINE_PROP_UINT8("timeren0-sel", arm_sp810_state, timeren0_sel,
> +                                                       SCCTRL_TIMER_REFCLK),
> +    DEFINE_PROP_UINT8("timeren1-sel", arm_sp810_state, timeren1_sel,
> +                                                       SCCTRL_TIMER_REFCLK),
> +    DEFINE_PROP_UINT8("timeren2-sel", arm_sp810_state, timeren2_sel,
> +                                                       SCCTRL_TIMER_REFCLK),
> +    DEFINE_PROP_UINT8("timeren3-sel", arm_sp810_state, timeren3_sel,
> +                                                       SCCTRL_TIMER_REFCLK),

Which input signals in the hardware do these properties
correspond to? I can't figure out what the mapping is.
As far as I can tell from the documentation the bits
in SCCTRL are just always reset to 0 and are not
controlled by external signals (which is what qdev
properties should typically correspond to).

thanks
-- PMM

Re: [Qemu-devel] [PATCH v3 1/2] hw/misc/arm_sp810: Create SP810 device

[Aggeler Fabian]

On 19 Aug 2014, at 16:03, Peter Maydell <peter.maydell@linaro.org> wrote:

> On 17 August 2014 15:24, Fabian Aggeler <aggelerf@ethz.ch> wrote:
>> This adds a device model for the PrimeXsys System Controller (SP810)
>> which is present in the Versatile Express motherboards. It is
>> so far read-only but allows to read the SCCTRL register.
>> 
>> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
>> ---
>> default-configs/arm-softmmu.mak |   1 +
>> hw/misc/Makefile.objs           |   1 +
>> hw/misc/arm_sp810.c             | 109 ++++++++++++++++++++++++++++++++++++++++
>> include/hw/misc/arm_sp810.h     |  80 +++++++++++++++++++++++++++++
>> 4 files changed, 191 insertions(+)
>> create mode 100644 hw/misc/arm_sp810.c
>> create mode 100644 include/hw/misc/arm_sp810.h
>> 
>> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
>> index f3513fa..67ba99a 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -55,6 +55,7 @@ CONFIG_PL181=y
>> CONFIG_PL190=y
>> CONFIG_PL310=y
>> CONFIG_PL330=y
>> +CONFIG_SP810=y
>> CONFIG_CADENCE=y
>> CONFIG_XGMAC=y
>> CONFIG_EXYNOS4=y
>> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
>> index 979e532..49d023b 100644
>> --- a/hw/misc/Makefile.objs
>> +++ b/hw/misc/Makefile.objs
>> @@ -13,6 +13,7 @@ common-obj-$(CONFIG_PL310) += arm_l2x0.o
>> common-obj-$(CONFIG_INTEGRATOR_DEBUG) += arm_integrator_debug.o
>> common-obj-$(CONFIG_A9SCU) += a9scu.o
>> common-obj-$(CONFIG_ARM11SCU) += arm11scu.o
>> +common-obj-$(CONFIG_SP810) += arm_sp810.o
> 
> We mostly don't use the 'arm' prefix (compare pl330, pl011,
> and other examples for other architectures), so you can
> remove it from filenames and variable names here.

Ok, will remove it then.
> 
>> 
>> # PKUnity SoC devices
>> common-obj-$(CONFIG_PUV3) += puv3_pm.o
>> diff --git a/hw/misc/arm_sp810.c b/hw/misc/arm_sp810.c
>> new file mode 100644
>> index 0000000..7aff9bd
>> --- /dev/null
>> +++ b/hw/misc/arm_sp810.c
>> @@ -0,0 +1,109 @@
>> +/*
>> + * ARM PrimeXsys System Controller (SP810)
>> + *
>> + * Copyright (C) 2014 Fabian Aggeler <aggelerf@ethz.ch>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>> +
>> +#include "hw/misc/arm_sp810.h"
>> +
>> +static const VMStateDescription vmstate_arm_sysctl = {
> 
> ^^^ should be vmstate_sp810.

Thanks for catching this. I will change it.
> 
>> +    .name = "arm_sp810",
>> +    .version_id = 1,
>> +    .minimum_version_id = 1,
>> +    .fields = (VMStateField[]) {
>> +        VMSTATE_UINT8(timeren0_sel, arm_sp810_state),
>> +        VMSTATE_UINT8(timeren1_sel, arm_sp810_state),
>> +        VMSTATE_UINT8(timeren2_sel, arm_sp810_state),
>> +        VMSTATE_UINT8(timeren3_sel, arm_sp810_state),
> 
> These are read only properties, so you don't need to save them.

Okay.

> 
>> +        VMSTATE_END_OF_LIST()
>> +    }
>> +};
>> +
>> +static uint64_t arm_sp810_read(void *opaque, hwaddr offset, unsigned size)
>> +{
>> +    arm_sp810_state *s = opaque;
>> +
>> +    switch (offset) {
>> +    case SCCTRL:
>> +        return (s->timeren3_sel << 21) | (s->timeren2_sel << 19)
>> +                | (s->timeren1_sel << 17) | (s->timeren0_sel << 15);
>> +    default:
>> +        qemu_log_mask(LOG_UNIMP,
>> +                "arm_sp810_read: Register not yet implemented: %s\n",
>> +                HWADDR_PRIx);
>> +        return 0;
>> +    }
>> +}
>> +
>> +static void arm_sp810_write(void *opaque, hwaddr offset,
>> +                            uint64_t val, unsigned size)
>> +{
>> +    switch (offset) {
>> +    default:
>> +        qemu_log_mask(LOG_UNIMP,
>> +                "arm_sp810_write: Register not yet implemented: %s\n",
>> +                HWADDR_PRIx);
>> +        return;
>> +    }
>> +}
>> +
>> +static const MemoryRegionOps arm_sp810_ops = {
>> +    .read = arm_sp810_read,
>> +    .write = arm_sp810_write,
>> +    .endianness = DEVICE_NATIVE_ENDIAN,
>> +};
>> +
>> +static void arm_sp810_init(Object *obj)
>> +{
>> +    arm_sp810_state *s = ARM_SP810(obj);
>> +
>> +    memory_region_init_io(&s->iomem, obj, &arm_sp810_ops, s, "arm-sp810",
>> +                          0x1000);
>> +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
>> +}
>> +
>> +static Property arm_sp810_properties[] = {
>> +    DEFINE_PROP_UINT8("timeren0-sel", arm_sp810_state, timeren0_sel,
>> +                                                       SCCTRL_TIMER_REFCLK),
>> +    DEFINE_PROP_UINT8("timeren1-sel", arm_sp810_state, timeren1_sel,
>> +                                                       SCCTRL_TIMER_REFCLK),
>> +    DEFINE_PROP_UINT8("timeren2-sel", arm_sp810_state, timeren2_sel,
>> +                                                       SCCTRL_TIMER_REFCLK),
>> +    DEFINE_PROP_UINT8("timeren3-sel", arm_sp810_state, timeren3_sel,
>> +                                                       SCCTRL_TIMER_REFCLK),
> 
> Which input signals in the hardware do these properties
> correspond to? I can't figure out what the mapping is.
> As far as I can tell from the documentation the bits
> in SCCTRL are just always reset to 0 and are not
> controlled by external signals (which is what qdev
> properties should typically correspond to).

Actually I don’t know how it is done in hardware. My goal was
to reflect the default speed of the SP804 timer in QEMU’s vexpress
emulation in the SCCTRL. What do you suggest in this case?
I could remove the QOM properties and set the reset value of the
TimerEnXSel bits in SCCTRL to 1 (TIMCLK) to match the SCCTRL 
with the speed of the SP804. 

Thanks,
Fabian

> 
> thanks
> -- PMM

Re: [Qemu-devel] [PATCH v3 1/2] hw/misc/arm_sp810: Create SP810 device

[Peter Maydell]

On 22 August 2014 09:38, Aggeler  Fabian <aggelerf@student.ethz.ch> wrote:
>
> On 19 Aug 2014, at 16:03, Peter Maydell <peter.maydell@linaro.org> wrote:
>> Which input signals in the hardware do these properties
>> correspond to? I can't figure out what the mapping is.
>> As far as I can tell from the documentation the bits
>> in SCCTRL are just always reset to 0 and are not
>> controlled by external signals (which is what qdev
>> properties should typically correspond to).
>
> Actually I don’t know how it is done in hardware. My goal was
> to reflect the default speed of the SP804 timer in QEMU’s vexpress
> emulation in the SCCTRL. What do you suggest in this case?

Well, fundamentally you have to find out what the hardware
does, and do that. We can't model anything else.

> I could remove the QOM properties and set the reset value of the
> TimerEnXSel bits in SCCTRL to 1 (TIMCLK) to match the SCCTRL
> with the speed of the SP804.

The h/w docs suggest the reset value is 0.
I have a feeling you may be attempting to make QEMU's
hardware model include behaviour which is the result of
firmware code setting register values before booting the
kernel...

thanks
-- PMM

Re: [Qemu-devel] [PATCH v3 1/2] hw/misc/arm_sp810: Create SP810 device

[Peter Crosthwaite]

On Fri, Aug 22, 2014 at 6:53 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 22 August 2014 09:38, Aggeler  Fabian <aggelerf@student.ethz.ch> wrote:
>>
>> On 19 Aug 2014, at 16:03, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> Which input signals in the hardware do these properties
>>> correspond to? I can't figure out what the mapping is.
>>> As far as I can tell from the documentation the bits
>>> in SCCTRL are just always reset to 0 and are not
>>> controlled by external signals (which is what qdev
>>> properties should typically correspond to).
>>
>> Actually I don’t know how it is done in hardware. My goal was
>> to reflect the default speed of the SP804 timer in QEMU’s vexpress
>> emulation in the SCCTRL. What do you suggest in this case?
>
> Well, fundamentally you have to find out what the hardware
> does, and do that. We can't model anything else.
>

With no actual clock muxing support it makes sense to me to pin the
register value to a hardwired setting. This as least allows a guest to
self-identify the one and only supported clocking setup without the
need for dummy firmware.

To do what the hardware does and have this value at it's docced reset
you would really want to add the clock frequency selection support
which means propagating the numbers through to timers etc making this
series much more complicated.

Regards,
Peter

>> I could remove the QOM properties and set the reset value of the
>> TimerEnXSel bits in SCCTRL to 1 (TIMCLK) to match the SCCTRL
>> with the speed of the SP804.
>
> The h/w docs suggest the reset value is 0.
> I have a feeling you may be attempting to make QEMU's
> hardware model include behaviour which is the result of
> firmware code setting register values before booting the
> kernel...
>
> thanks
> -- PMM
>