From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38812) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XJJZZ-0000LP-0g for qemu-devel@nongnu.org; Mon, 18 Aug 2014 05:49:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XJJZU-0007tN-7b for qemu-devel@nongnu.org; Mon, 18 Aug 2014 05:49:52 -0400 Received: from mail-pa0-x22e.google.com ([2607:f8b0:400e:c03::22e]:34610) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XJJZU-0007tI-0o for qemu-devel@nongnu.org; Mon, 18 Aug 2014 05:49:48 -0400 Received: by mail-pa0-f46.google.com with SMTP id lj1so7443884pab.33 for ; Mon, 18 Aug 2014 02:49:45 -0700 (PDT) From: "Edgar E. Iglesias" Date: Mon, 18 Aug 2014 19:40:29 +1000 Message-Id: <1408354830-1143-10-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1408354830-1143-1-git-send-email-edgar.iglesias@gmail.com> References: <1408354830-1143-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v5 09/10] target-arm: Add IRQ and FIQ routing to EL2 and 3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 12 ++++++++++++ target-arm/helper.c | 14 ++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 683fd44..8ad23fa 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1153,6 +1153,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_pl(env); unsigned int target_el = arm_excp_target_el(cs, excp_idx); + /* FIXME: Use actual secure state. */ + bool secure = false; + /* Interrupts can only be hypervised and routed to + * EL2 if we are in NS EL0/1. + */ + bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2; /* Don't take exceptions if they target a lower EL. */ if (cur_el > target_el) { @@ -1161,8 +1167,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) switch (excp_idx) { case EXCP_FIQ: + if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) { + return true; + } return !(env->daif & PSTATE_F); case EXCP_IRQ: + if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) { + return true; + } return ((IS_M(env) && env->regs[15] < 0xfffffff0) || !(env->daif & PSTATE_I)); default: diff --git a/target-arm/helper.c b/target-arm/helper.c index a2205d1..976fd89 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3339,6 +3339,20 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) target_el = 2; } break; + case EXCP_FIQ: + case EXCP_IRQ: + { + const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO; + const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ; + + if (!secure && (env->cp15.hcr_el2 & hcr_mask)) { + target_el = 2; + } + if (env->cp15.scr_el3 & scr_mask) { + target_el = 3; + } + break; + } } return target_el; } -- 1.9.1