From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com,
aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com,
greg.bellows@linaro.org, pbonzini@redhat.com,
alex.bennee@linaro.org, christoffer.dall@linaro.org,
rth@twiddle.net
Subject: [Qemu-devel] [PATCH v5 04/10] target-arm: Break out exception masking to a separate func
Date: Mon, 18 Aug 2014 19:40:24 +1000 [thread overview]
Message-ID: <1408354830-1143-5-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1408354830-1143-1-git-send-email-edgar.iglesias@gmail.com>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
cpu-exec.c | 5 ++---
target-arm/cpu.h | 15 +++++++++++++++
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index c6aad74..f9c0ebc 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -595,7 +595,7 @@ int cpu_exec(CPUArchState *env)
}
#elif defined(TARGET_ARM)
if (interrupt_request & CPU_INTERRUPT_FIQ
- && !(env->daif & PSTATE_F)) {
+ && arm_excp_unmasked(cpu, EXCP_FIQ)) {
cpu->exception_index = EXCP_FIQ;
cc->do_interrupt(cpu);
next_tb = 0;
@@ -610,8 +610,7 @@ int cpu_exec(CPUArchState *env)
We avoid this by disabling interrupts when
pc contains a magic address. */
if (interrupt_request & CPU_INTERRUPT_HARD
- && ((IS_M(env) && env->regs[15] < 0xfffffff0)
- || !(env->daif & PSTATE_I))) {
+ && arm_excp_unmasked(cpu, EXCP_IRQ)) {
cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 48efe23..ffcfb10 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1146,6 +1146,21 @@ bool write_cpustate_to_list(ARMCPU *cpu);
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
+{
+ CPUARMState *env = cs->env_ptr;
+
+ switch (excp_idx) {
+ case EXCP_FIQ:
+ return !(env->daif & PSTATE_F);
+ case EXCP_IRQ:
+ return ((IS_M(env) && env->regs[15] < 0xfffffff0)
+ || !(env->daif & PSTATE_I));
+ default:
+ g_assert_not_reached();
+ }
+}
+
static inline CPUARMState *cpu_init(const char *cpu_model)
{
ARMCPU *cpu = cpu_arm_init(cpu_model);
--
1.9.1
next prev parent reply other threads:[~2014-08-18 9:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-18 9:40 [Qemu-devel] [PATCH v5 00/10] target-arm: Parts of the AArch64 EL2/3 exception model Edgar E. Iglesias
2014-08-18 9:40 ` [Qemu-devel] [PATCH v5 01/10] target-arm: Add HCR_EL2 Edgar E. Iglesias
2014-08-19 14:58 ` Peter Maydell
2014-08-18 9:40 ` [Qemu-devel] [PATCH v5 02/10] target-arm: Add SCR_EL3 Edgar E. Iglesias
2014-08-19 15:13 ` Peter Maydell
2014-08-18 9:40 ` [Qemu-devel] [PATCH v5 03/10] target-arm: A64: Refactor aarch64_cpu_do_interrupt Edgar E. Iglesias
2014-08-18 9:40 ` Edgar E. Iglesias [this message]
2014-08-18 9:40 ` [Qemu-devel] [PATCH v5 05/10] target-arm: Don't take interrupts targeting lower ELs Edgar E. Iglesias
2014-08-18 9:40 ` [Qemu-devel] [PATCH v5 06/10] target-arm: A64: Correct updates to FAR and ESR on exceptions Edgar E. Iglesias
2014-08-18 9:40 ` [Qemu-devel] [PATCH v5 07/10] target-arm: A64: Emulate the HVC insn Edgar E. Iglesias
2014-08-18 9:40 ` [Qemu-devel] [PATCH v5 08/10] target-arm: A64: Emulate the SMC insn Edgar E. Iglesias
2014-08-18 9:40 ` [Qemu-devel] [PATCH v5 09/10] target-arm: Add IRQ and FIQ routing to EL2 and 3 Edgar E. Iglesias
2014-08-18 9:40 ` [Qemu-devel] [PATCH v5 10/10] target-arm: Add support for VIRQ and VFIQ Edgar E. Iglesias
2014-09-09 19:16 ` [Qemu-devel] [PATCH v5 00/10] target-arm: Parts of the AArch64 EL2/3 exception model Peter Maydell
2014-09-09 22:33 ` Edgar E. Iglesias
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