From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XJJWC-00043E-4v for qemu-devel@nongnu.org; Mon, 18 Aug 2014 05:46:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XJJW7-0007Hg-BW for qemu-devel@nongnu.org; Mon, 18 Aug 2014 05:46:24 -0400 Received: from mail-pd0-x22a.google.com ([2607:f8b0:400e:c02::22a]:64363) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XJJW7-0007Ha-3S for qemu-devel@nongnu.org; Mon, 18 Aug 2014 05:46:19 -0400 Received: by mail-pd0-f170.google.com with SMTP id g10so7274959pdj.29 for ; Mon, 18 Aug 2014 02:46:17 -0700 (PDT) From: "Edgar E. Iglesias" Date: Mon, 18 Aug 2014 19:40:24 +1000 Message-Id: <1408354830-1143-5-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1408354830-1143-1-git-send-email-edgar.iglesias@gmail.com> References: <1408354830-1143-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v5 04/10] target-arm: Break out exception masking to a separate func List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias --- cpu-exec.c | 5 ++--- target-arm/cpu.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index c6aad74..f9c0ebc 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -595,7 +595,7 @@ int cpu_exec(CPUArchState *env) } #elif defined(TARGET_ARM) if (interrupt_request & CPU_INTERRUPT_FIQ - && !(env->daif & PSTATE_F)) { + && arm_excp_unmasked(cpu, EXCP_FIQ)) { cpu->exception_index = EXCP_FIQ; cc->do_interrupt(cpu); next_tb = 0; @@ -610,8 +610,7 @@ int cpu_exec(CPUArchState *env) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->daif & PSTATE_I))) { + && arm_excp_unmasked(cpu, EXCP_IRQ)) { cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 48efe23..ffcfb10 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1146,6 +1146,21 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) +{ + CPUARMState *env = cs->env_ptr; + + switch (excp_idx) { + case EXCP_FIQ: + return !(env->daif & PSTATE_F); + case EXCP_IRQ: + return ((IS_M(env) && env->regs[15] < 0xfffffff0) + || !(env->daif & PSTATE_I)); + default: + g_assert_not_reached(); + } +} + static inline CPUARMState *cpu_init(const char *cpu_model) { ARMCPU *cpu = cpu_arm_init(cpu_model); -- 1.9.1