From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 12/19] target-arm: Implement MDSCR_EL1 as having state
Date: Tue, 19 Aug 2014 19:09:37 +0100 [thread overview]
Message-ID: <1408471784-2652-13-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1408471784-2652-1-git-send-email-peter.maydell@linaro.org>
Now that all the new code to support single-stepping is in
place, wire up the guest-visible MDSCR_EL1, so the guest
can enable single-stepping.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-arm/helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f981569..2a77c97 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2204,7 +2204,9 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
*/
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
+ .resetvalue = 0 },
/* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
{ .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
--
1.9.1
next prev parent reply other threads:[~2014-08-19 18:11 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-19 18:09 [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 01/19] target-arm: Fix return address for A64 BRK instructions Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 02/19] target-arm: Collect up the debug cp register definitions Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 03/19] target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14 Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 04/19] target-arm: Provide both 32 and 64 bit versions of debug registers Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 05/19] target-arm: Adjust debug ID registers per-CPU Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 06/19] target-arm: Don't allow AArch32 to access RES0 CPSR bits Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 07/19] target-arm: Correctly handle PSTATE.SS when taking exception to AArch32 Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 08/19] target-arm: Set PSTATE.SS correctly on exception return from AArch64 Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 09/19] target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 10/19] target-arm: Implement ARMv8 single-step handling for A64 code Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 11/19] target-arm: Implement ARMv8 single-stepping for AArch32 code Peter Maydell
2014-08-19 18:09 ` Peter Maydell [this message]
2014-08-19 18:09 ` [Qemu-devel] [PULL 13/19] target-arm: Rename QEMU PSCI v0.1 definitions Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 14/19] arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 15/19] arm: cortex-a9: Fix cache-line size and associativity Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 16/19] loader: Add load_image_gzipped function Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 17/19] aarch64: Allow -kernel option to take a gzip-compressed kernel Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 18/19] arm: armv7m: Rename address_space_mem -> system_memory Peter Maydell
2014-08-19 18:09 ` [Qemu-devel] [PULL 19/19] arm: stellaris: Remove misleading address_space_mem var Peter Maydell
2014-08-20 9:49 ` [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1408471784-2652-13-git-send-email-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).