[Qemu-devel] [PATCH 00/15] target-arm: Add GICv1/SecExt and GICv2/Grouping

[Fabian Aggeler <aggelerf@ethz.ch>]

Hi,

this series adds GICv1 Security Extensions (secure/non-secure interrupts)
and interrupt grouping of the GICv2 specification. The patches use the 
terminology introduced by GICv2 (Group0 instead of secure). 
The series first adds FIQ lines from the GIC to the CPUs and then adds 
the Security Extensions. As the Security Extensions for CPUs are not 
upstream yet a ns_access() stub is used, which can be replaced in a 
follow-up with the actual implementation to determine the security state
of a read/write access (needed for banking).

Any feedback is highly appreciated!

Thanks,
Fabian

Fabian Aggeler (15):
  hw/intc/arm_gic: Request FIQ sources
  hw/arm/vexpress.c: Wire FIQ between CPU <> GIC
  hw/intc/arm_gic: Add Security Extensions property
  hw/intc/arm_gic: Add ns_access() function
  hw/intc/arm_gic: Add Interrupt Group Registers
  hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked
  hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked
  hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked
  hw/intc/arm_gic: Implement Non-secure view of RPR
  hw/intc/arm_gic: Handle grouping for GICC_HPPIR
  hw/intc/arm_gic: Change behavior of EOIR writes
  hw/intc/arm_gic: Change behavior of IAR writes
  hw/intc/arm_gic: Restrict priority view
  hw/intc/arm_gic: Break out gic_update() function
  hw/intc/arm_gic: add gic_update() for grouping

 hw/arm/vexpress.c                |   2 +
 hw/intc/arm_gic.c                | 422 ++++++++++++++++++++++++++++++++++++---
 hw/intc/arm_gic_common.c         |   9 +-
 hw/intc/arm_gic_kvm.c            |   8 +-
 hw/intc/armv7m_nvic.c            |   2 +-
 hw/intc/gic_internal.h           |  25 +++
 include/hw/intc/arm_gic_common.h |  20 +-
 7 files changed, 447 insertions(+), 41 deletions(-)

-- 
1.8.3.2