From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKm6x-0001zo-Ca for qemu-devel@nongnu.org; Fri, 22 Aug 2014 06:30:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XKm6n-00047z-Lv for qemu-devel@nongnu.org; Fri, 22 Aug 2014 06:30:23 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:57019) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKm6n-00047W-FU for qemu-devel@nongnu.org; Fri, 22 Aug 2014 06:30:13 -0400 From: Fabian Aggeler Date: Fri, 22 Aug 2014 12:29:40 +0200 Message-ID: <1408703392-23893-4-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1408703392-23893-1-git-send-email-aggelerf@ethz.ch> References: <1408703392-23893-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 03/15] hw/intc/arm_gic: Add Security Extensions property List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, greg.bellows@linaro.org, christoffer.dall@linaro.org, edgar.iglesias@gmail.com The existing implementation does not support Security Extensions mentioned in the GICv1 and GICv2 architecture specification. Security Extensions are not available on all GICs. This property makes it possible to enable Security Extensions. It also makes GICD_TYPER/ICDICTR.SecurityExtn RAO for GICs which implement Security Extensions. Signed-off-by: Fabian Aggeler --- hw/intc/arm_gic.c | 5 ++++- hw/intc/arm_gic_common.c | 1 + include/hw/intc/arm_gic_common.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index b27bd0e..75b5121 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -297,7 +297,10 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) if (offset == 0) return s->enabled; if (offset == 4) - return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); + /* Interrupt Controller Type Register */ + return ((s->num_irq / 32) - 1) + | ((NUM_CPU(s) - 1) << 5) + | (s->security_extn << 10); if (offset < 0x08) return 0; if (offset >= 0x80) { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 6d884ec..302a056 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -149,6 +149,7 @@ static Property arm_gic_common_properties[] = { * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) */ DEFINE_PROP_UINT32("revision", GICState, revision, 1), + DEFINE_PROP_UINT8("security-extn", GICState, security_extn, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 01c6f24..4e25017 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -105,6 +105,7 @@ typedef struct GICState { MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ uint32_t num_irq; uint32_t revision; + uint8_t security_extn; int dev_fd; /* kvm device fd if backed by kvm vgic support */ } GICState; -- 1.8.3.2