From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50042) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XLzuT-0005QY-3I for qemu-devel@nongnu.org; Mon, 25 Aug 2014 15:26:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XLzuN-0002LH-0x for qemu-devel@nongnu.org; Mon, 25 Aug 2014 15:26:33 -0400 From: Tom Musta Date: Mon, 25 Aug 2014 14:25:43 -0500 Message-Id: <1408994744-17312-6-git-send-email-tommusta@gmail.com> In-Reply-To: <1408994744-17312-1-git-send-email-tommusta@gmail.com> References: <1408994744-17312-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 5/6] target-ppc: Clean up mullwo List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Tom Musta , agraf@suse.de, rth@twiddle.net Simplify the implementation of mullwo. For 64 bit CPUs, the result is the concatenation of the upper and lower parts of the muls2_i32 operation, which may be slightly better than deposit. For 32 bit CPUs, the lower part of the muls_i32 operation is moved into the target GPR. Signed-off-by: Tom Musta Suggested-by: Richard Henderson --- target-ppc/translate.c | 11 +++-------- 1 files changed, 3 insertions(+), 8 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ced295f..1062634 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1150,19 +1150,14 @@ static void gen_mullwo(DisasContext *ctx) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); -#if defined(TARGET_PPC64) - TCGv_i64 t2 = tcg_temp_new_i64(); -#endif tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); tcg_gen_muls2_i32(t0, t1, t0, t1); - tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); #if defined(TARGET_PPC64) - tcg_gen_ext_i32_tl(t2, t1); - tcg_gen_deposit_i64(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rD(ctx->opcode)], t2, 32, 32); - tcg_temp_free(t2); + tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); +#else + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); #endif tcg_gen_sari_i32(t0, t0, 31); -- 1.7.1