From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38061) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNKGc-0007eG-Ar for qemu-devel@nongnu.org; Fri, 29 Aug 2014 07:23:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XNKGU-000736-Vs for qemu-devel@nongnu.org; Fri, 29 Aug 2014 07:22:54 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46718) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNKGU-00070y-Oh for qemu-devel@nongnu.org; Fri, 29 Aug 2014 07:22:46 -0400 From: Peter Maydell Date: Fri, 29 Aug 2014 12:21:22 +0100 Message-Id: <1409311292-18860-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 00/10] Implement ARM architectural watchpoints List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org These patches implement support for the ARM architecturally defined watchpoints, for ARMv8 and ARMv7 CPUs. The first three patches improve the generic exec.c watchpoint code to provide some features that ARM watchpoints require. Patch 4 is a cleanup that makes an ad-hoc per-target registered callback function a proper QOM method (Andreas, I cc'd you on this series in case you wanted to review this one.) Patches 5..10 do the actual work. There are a couple of slight corner cases we don't currently implement: * LDRT/STRT from kernel mode are supposed to trigger watchpoints set to fire on user mode accesses. This would require some effort to plumb the mmu_idx through into the watchpoint-check callbacks in exec.c, and Linux doesn't use it. * the cache-invalidate instruction DC IVAC strictly speaking should trigger watchpoints, but we currently just NOP that so it won't. but all the functionality Linux uses works fine. Tested: v7 kernel, v8 kernel with 64-bit gdbserver, v8 kernel with 32-bit gdbserver using the compat interface. (A kernel bug means 32-bit compat will incorrectly report watchpoint hits to gdb as SIGTRAP. A proposed fix for this is here: https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/commit/?h=fixes/core&id=27d7ff273c2aad37b28f6ff0cab2cfa35b51e648 and will presumably make its way into upstream kernels.) Peter Maydell (10): exec.c: Relax restrictions on watchpoint length and alignment exec.c: Provide full set of dummy wp remove functions in user-mode exec.c: Record watchpoint fault address and direction cpu-exec: Make debug_excp_handler a QOM CPU method target-arm: Implement setting of watchpoints target-arm: Move extended_addresses_enabled() to internals.h target-arm: Implement handling of fired watchpoints target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32 target-arm: Remove comment about MDSCR_EL1 being dummy implementation target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0 cpu-exec.c | 13 +--- exec.c | 61 +++++++++++---- include/exec/exec-all.h | 4 - include/qom/cpu.h | 10 ++- linux-user/main.c | 3 +- qom/cpu.c | 5 ++ target-arm/cpu.c | 3 + target-arm/cpu.h | 2 + target-arm/helper.c | 202 +++++++++++++++++++++++++++++++++++++++++++----- target-arm/internals.h | 30 +++++++ target-arm/machine.c | 3 + target-arm/op_helper.c | 188 ++++++++++++++++++++++++++++++++++++++++++++ target-i386/cpu.c | 6 +- target-i386/cpu.h | 2 +- target-i386/helper.c | 5 +- target-lm32/cpu.c | 2 +- target-lm32/cpu.h | 2 +- target-lm32/helper.c | 5 +- target-xtensa/cpu.c | 2 +- target-xtensa/cpu.h | 2 +- target-xtensa/helper.c | 5 +- 21 files changed, 491 insertions(+), 64 deletions(-) -- 1.9.1