From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNKGY-0007eA-Bo for qemu-devel@nongnu.org; Fri, 29 Aug 2014 07:22:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XNKGT-00072a-In for qemu-devel@nongnu.org; Fri, 29 Aug 2014 07:22:50 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46718) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNKGT-00070y-CG for qemu-devel@nongnu.org; Fri, 29 Aug 2014 07:22:45 -0400 From: Peter Maydell Date: Fri, 29 Aug 2014 12:21:31 +0100 Message-Id: <1409311292-18860-10-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1409311292-18860-1-git-send-email-peter.maydell@linaro.org> References: <1409311292-18860-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 09/10] target-arm: Remove comment about MDSCR_EL1 being dummy implementation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org MDSCR_EL1 has actual functionality now; remove the out of date comment that claims it is a dummy implementation. Signed-off-by: Peter Maydell --- target-arm/helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index ef1eac9..6ae3c50 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2188,9 +2188,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, - /* Dummy implementation of monitor debug system control register: - * we don't support debug. (The 32-bit alias is DBGDSCRext.) - */ + /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, .access = PL1_RW, -- 1.9.1