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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 10/16] target-arm: Make the ARM PMCCNTR register 64-bit
Date: Fri, 29 Aug 2014 15:37:22 +0100	[thread overview]
Message-ID: <1409323049-19255-11-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1409323049-19255-1-git-send-email-peter.maydell@linaro.org>

From: Alistair Francis <alistair.francis@xilinx.com>

This makes the PMCCNTR register 64-bit to allow for the
64-bit ARMv8 version.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 6c5bac5fd0ea54963b1fc0e7f9464909f2e19a73.1409025949.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu.h    |  2 +-
 target-arm/helper.c | 19 +++++++++----------
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 659b104..986c249 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -224,7 +224,7 @@ typedef struct CPUARMState {
         /* If the counter is enabled, this stores the last time the counter
          * was reset. Otherwise it stores the counter value
          */
-        uint32_t c15_ccnt;
+        uint64_t c15_ccnt;
     } cp15;
 
     struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2a77c97..711ca12 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -551,11 +551,10 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                        uint64_t value)
 {
-    /* Don't computer the number of ticks in user mode */
-    uint32_t temp_ticks;
+    uint64_t temp_ticks;
 
-    temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
-                  get_ticks_per_sec() / 1000000;
+    temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
+                          get_ticks_per_sec(), 1000000);
 
     if (env->cp15.c9_pmcr & PMCRE) {
         /* If the counter is enabled */
@@ -587,15 +586,15 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    uint32_t total_ticks;
+    uint64_t total_ticks;
 
     if (!(env->cp15.c9_pmcr & PMCRE)) {
         /* Counter is disabled, do not change value */
         return env->cp15.c15_ccnt;
     }
 
-    total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
-                  get_ticks_per_sec() / 1000000;
+    total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
+                           get_ticks_per_sec(), 1000000);
 
     if (env->cp15.c9_pmcr & PMCRD) {
         /* Increment once every 64 processor clock cycles */
@@ -607,7 +606,7 @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
 {
-    uint32_t total_ticks;
+    uint64_t total_ticks;
 
     if (!(env->cp15.c9_pmcr & PMCRE)) {
         /* Counter is disabled, set the absolute value */
@@ -615,8 +614,8 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         return;
     }
 
-    total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
-                  get_ticks_per_sec() / 1000000;
+    total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
+                           get_ticks_per_sec(), 1000000);
 
     if (env->cp15.c9_pmcr & PMCRD) {
         /* Increment once every 64 processor clock cycles */
-- 
1.9.1

  parent reply	other threads:[~2014-08-29 14:37 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-29 14:37 [Qemu-devel] [PULL 00/16] target-arm queue Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 01/16] disas/libvixl: Update to upstream VIXL 1.5 Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 02/16] target-arm: Fix regression that disabled VFP for ARMv5 CPUs Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 03/16] target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 04/16] arm_gic: Fix read of GICD_ICFGR Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 05/16] arm_gic: GICD_ICFGR: Write model only for pre v1 GICs Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 06/16] arm_gic: Do not force PPIs to edge-triggered mode Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 07/16] arm_gic: Use GIC_NR_SGIS constant Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 08/16] aarch64: raise max_cpus to 8 Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 09/16] hw/intc/arm_gic: honor target mask in gic_update() Peter Maydell
2014-08-29 14:37 ` Peter Maydell [this message]
2014-08-29 14:37 ` [Qemu-devel] [PULL 11/16] arm: Implement PMCCNTR 32b read-modify-write Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 12/16] target-arm: Implement PMCCNTR_EL0 and related registers Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 13/16] target-arm: Add arm_ccnt_enabled function Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 14/16] target-arm: Implement pmccntr_sync function Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 15/16] target-arm: Remove old code and replace with new functions Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 16/16] target-arm: Implement pmccfiltr_write function Peter Maydell
2014-08-29 15:46 ` [Qemu-devel] [PULL 00/16] target-arm queue Peter Maydell

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