From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNNJ5-00077Z-3M for qemu-devel@nongnu.org; Fri, 29 Aug 2014 10:37:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XNNIy-00081e-0w for qemu-devel@nongnu.org; Fri, 29 Aug 2014 10:37:39 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46762) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNNIx-000805-Q9 for qemu-devel@nongnu.org; Fri, 29 Aug 2014 10:37:31 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XNNIv-00051u-K2 for qemu-devel@nongnu.org; Fri, 29 Aug 2014 15:37:29 +0100 From: Peter Maydell Date: Fri, 29 Aug 2014 15:37:23 +0100 Message-Id: <1409323049-19255-12-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1409323049-19255-1-git-send-email-peter.maydell@linaro.org> References: <1409323049-19255-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 11/16] arm: Implement PMCCNTR 32b read-modify-write List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Peter Crosthwaite The register is now 64bit, however a 32 bit write to the register should leave the higher bits unchanged. The open coded write handler does not implement this, so we need to read-modify-write accordingly. Signed-off-by: Peter Crosthwaite Reviewed-by: Alistair Francis Message-id: ec350573424bb2adc1701c3b9278d26598e2f2d1.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- target-arm/helper.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 711ca12..0d2ee41 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -623,6 +623,15 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, } env->cp15.c15_ccnt = total_ticks - value; } + +static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t cur_val = pmccntr_read(env, NULL); + + pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); +} + #endif static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -754,7 +763,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { #ifndef CONFIG_USER_ONLY { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, - .readfn = pmccntr_read, .writefn = pmccntr_write, + .readfn = pmccntr_read, .writefn = pmccntr_write32, .accessfn = pmreg_access }, #endif { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, -- 1.9.1